Programming languages used in this repository

  •   VHDL
    61.45 %
  •   SystemVerilog
    20.45 %
  •   Python
    12.98 %
  •   C
    3.11 %
  •   Verilog
    1.94 %
  •   Makefile
    0.08 %

Commit statistics for master Jun 28 - Sep 14

  • Total: 191 commits
  • Average per day: 0.4 commits
  • Authors: 1

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