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FMC DEL 1ns 2cha
Commit a3dc2ea8 authored by Tom Levens's avatar Tom Levens
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Port to latest SVEC reference design 

References:
    https://gitlab.cern.ch/be-cem-edl/fec/hardware-modules/svec
    https://gitlab.cern.ch/be-cem-edl/fec/hardware-modules/wrtd-reference-designs
parent 0ca74d29
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.gitmodules
View file @ a3dc2ea8
......@@ -2,13 +2,16 @@
path = hdl/ip_cores/general-cores
url = https://ohwr.org/project/general-cores.git
branch = proposed_master
[submodule "hdl/ip_cores/wishbone-gen"]
path = hdl/ip_cores/wishbone-gen
url = https://ohwr.org/project/wishbone-gen.git
[submodule "hdl/ip_cores/uvm_agents"]
path = hdl/ip_cores/uvm_agents
url = https://github.com/AakaFosfor/uvm_agents.git
[submodule "hdl/ip_cores/vme64x-core"]
path = hdl/ip_cores/vme64x-core
url = https://ohwr.org/project/vme64x-core.git
branch = proposed_master
[submodule "hdl/ip_cores/svec"]
path = hdl/ip_cores/svec
url = https://ohwr.org/project/svec.git
[submodule "hdl/ip_cores/wr-cores"]
path = hdl/ip_cores/wr-cores
url = https://ohwr.org/project/wr-cores.git
[submodule "hdl/ip_cores/ddr3-sp6-core"]
path = hdl/ip_cores/ddr3-sp6-core
url = https://ohwr.org/project/ddr3-sp6-core.git
hdl/ffpg/rtl/Ad9512Control.vhd
View file @ a3dc2ea8
......@@ -386,7 +386,7 @@ begin
wb_cyc_i => WbStb,
wb_ack_o => WbAck,
wb_err_o => open,
wb_int_o => WbInt,
int_o => WbInt,
ss_pad_o => SpiAd9512Cs_n,
sclk_pad_o => SpiAd9512Sclk_o,
mosi_pad_o => SpiAd9512Mosi_o,
......
hdl/ffpg/rtl/FfpgCore.vhd
View file @ a3dc2ea8
......@@ -292,7 +292,6 @@ begin
CnxMasterIn(c_SlaveAd9512Id).err <= '0';
CnxMasterIn(c_SlaveAd9512Id).rty <= '0';
CnxMasterIn(c_SlaveAd9512Id).stall <= '0';
CnxMasterIn(c_SlaveAd9512Id).int <= '0';
SpiAd9512CsWb_n <= ChipSelect_b32(0);
----------------------------------
......
hdl/ffpg/rtl/FfpgPkg.vhd
View file @ a3dc2ea8
......@@ -40,9 +40,9 @@ use work.wishbone_pkg.all;
package FfpgPkg is
constant VersionMajor: natural := 1;
constant VersionMinor: natural := 4;
constant VersionRevision: natural := 2;
constant VersionMajor: natural := 2;
constant VersionMinor: natural := 0;
constant VersionRevision: natural := 0;
type t_Ad5600Interface is record
FrameSynchronization_n: std_logic;
......
hdl/ffpg/rtl/Manifest.py
View file @ a3dc2ea8
......@@ -2,8 +2,28 @@ files = [
"ffpg_csr.vhd",
"ffpg_csr_pkg.vhd",
"FfpgCore.vhd",
"FfpgCorePkg.vhd",
"../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd"
"FfpgPkg.vhd",
"FfpgSlave.vhd",
"Ad9512Control.vhd",
"Ad9512Syncer.vhd",
"ChangeDetector.vhd",
"CounterLength.vhd",
"Counter.vhd",
"DacsController.vhd",
"DelayController.vhd",
"DelayedPulseGenerator/DelayedPulseGeneratorFsm.vhd",
"DelayedPulseGenerator/DelayedPulseGeneratorsCdc.vhd",
"DelayedPulseGenerator/DelayedPulseGenerator.vhd",
"Delay.vhd",
"EdgeDetector.vhd",
"FrequencySense.vhd",
"PulseGeneratorTime.vhd",
"PulseGenerator.vhd",
"RegSyncer.vhd",
"Reg.vhd",
"ResetSyncer.vhd",
"ShiftRegister.vhd",
"SlowToggle.vhd",
"SpiMasterWb.v",
"WbSlaveWrapper.vhd",
]
modules = { "local" : ["../../ip_cores/wishbone-gen/lib"]}
hdl/ffpg/rtl/WbSlaveWrapper.vhd
View file @ a3dc2ea8
......@@ -138,7 +138,6 @@ begin
);
Wb_o.err <= '0';
Wb_o.rty <= '0';
Wb_o.int <= '0';
-- local registers for LOAD_EXT fields
pLocalRegs: process (Clk_ik) is begin
......
ddr3-sp6-core @ 01a07e1d
Subproject commit 01a07e1d6d118c0a9afc4a4a3c009bfc2027abca
general-cores @ 902c347a
Subproject commit 0d75c0fdc0059b9ce3a8adb76a4ff14b5b795d6c
Subproject commit 902c347af55ae3c4c3e19ba6646b0cd83f76a8e8
svec @ 190e95de
Subproject commit 190e95decc6f79b14eb34761bf28f600e9063e24
uvm_agents @ 0b05a55f
Subproject commit 0b05a55f2b73ecd210f7de4e278c394e314bb5f9
vme64x-core @ a0ca042e
Subproject commit 52d537441e6187619dee7b908534d72408cc03f0
Subproject commit a0ca042e1f3c19a81c3594477c0c811ac761aaa4
wishbone-gen @ 8d431e7f
Subproject commit 8d431e7f4dbd9e2423b3207267c7495df64e27b0
hdl/ip_cores/wishbone-gen_patches/0001-updated-README-wbgen2-seems-not-to-work-in-Lua-5.1.x.patch deleted 100644 → 0
View file @ 0ca74d29
From dabd1b3d6d05cc844ae576701b69b0a535be1748 Mon Sep 17 00:00:00 2001
From: Jan Pospisil <j.pospisil@cern.ch>
Date: Wed, 24 Aug 2016 18:43:20 +0200
Subject: [PATCH 1/7] updated README - wbgen2 seems not to work in Lua > 5.1.x
---
README | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/README b/README
index 6081554..705c954 100644
--- a/README
+++ b/README
@@ -1,4 +1,4 @@
-This is the initial version of wbgen2. Requires Lua 5.1.4+. Enjoy it :)
+This is the initial version of wbgen2. Requires Lua 5.1.x (not 5.2.x and newer). Enjoy it :)
Compilation instructions:
Just type "make" in the main directory of wbgen2. The resulting file will be "wbgen2".
--
2.8.1.windows.1
hdl/ip_cores/wishbone-gen_patches/0002-added-an-error-for-unsupported-Verilog-option.patch deleted 100644 → 0
View file @ 0ca74d29
From 6fac46f32b9791f6041a8aa7900dc125c11faa4c Mon Sep 17 00:00:00 2001
From: Jan Pospisil <j.pospisil@cern.ch>
Date: Wed, 24 Aug 2016 18:44:54 +0200
Subject: [PATCH 2/7] added an error for unsupported Verilog option
---
wbgen_main.lua | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/wbgen_main.lua b/wbgen_main.lua
index 02fb2ec..9dfec6e 100644
--- a/wbgen_main.lua
+++ b/wbgen_main.lua
@@ -18,7 +18,13 @@
-- MA 02111-1307, USA.
--
-wbgen2_version="0.6.1-alpha"
+--------------------------------------------------------------------------------
+-- Modifications:
+-- 2016-08-24: by Jan Pospisil (j.pospisil@cern.ch)
+-- * added an error for unsupported Verilog option
+--------------------------------------------------------------------------------
+
+wbgen2_version="0.6.2-alpha"
options = {};
options.reset_type = "asynchronous";
@@ -191,6 +197,7 @@ if(options.output_hdl_file ~= nil) then
if (options.lang == "vhdl") then
cgen_generate_vhdl_code(tree);
elseif (options.lang == "verilog") then
+ die("Verilog option is not supported")
-- cgen_generate_verilog_code(tree);
end
end
--
2.8.1.windows.1
hdl/ip_cores/wishbone-gen_patches/0003-better-indent-for-VHDL-package.patch deleted 100644 → 0
View file @ 0ca74d29
From 09e2f21902515eb35c19b75f0550b034a20c1165 Mon Sep 17 00:00:00 2001
From: Jan Pospisil <j.pospisil@cern.ch>
Date: Wed, 24 Aug 2016 19:09:21 +0200
Subject: [PATCH 3/7] better indent for VHDL package
---
cgen_common.lua | 12 +++++++++---
cgen_vhdl.lua | 47 ++++++++++++++++++++++++++++++++++++++---------
2 files changed, 47 insertions(+), 12 deletions(-)
diff --git a/cgen_common.lua b/cgen_common.lua
index dca15cd..7c77c7a 100644
--- a/cgen_common.lua
+++ b/cgen_common.lua
@@ -5,6 +5,11 @@
-- CERN BE-CO-HT
-- LICENSED UNDER GPL v2
+--------------------------------------------------------------------------------
+-- Modifications:
+-- 2016-08-24: by Jan Pospisil (j.pospisil@cern.ch)
+-- * better indent for VHDL package
+--------------------------------------------------------------------------------
------------------------------
-- HDL syntax tree constructors
@@ -345,6 +350,9 @@ function indent_zero()
end
function indent_left()
+ if cur_indent <= 0 then
+ die("internal error - unmatched indent")
+ end
cur_indent = cur_indent - 1;
end
@@ -363,9 +371,7 @@ function emiti()
end
function emit(s)
- local i;
-
- for i = 1,cur_indent do emit_code=emit_code.." "; end
+ emiti();
emit_code=emit_code..s.."\n";
end
diff --git a/cgen_vhdl.lua b/cgen_vhdl.lua
index 80e91c9..1bafa9b 100644
--- a/cgen_vhdl.lua
+++ b/cgen_vhdl.lua
@@ -8,6 +8,12 @@
-- The VHDL code generator.
--
+--------------------------------------------------------------------------------
+-- Modifications:
+-- 2016-08-24: by Jan Pospisil (j.pospisil@cern.ch)
+-- * better indent for VHDL package
+--------------------------------------------------------------------------------
+
-- conversion table between VHDL data types and wbgen2 internal data types
fieldtype_2_vhdl={};
fieldtype_2_vhdl[BIT]="std_logic";
@@ -69,13 +75,11 @@ function cgen_vhdl_package()
local pkg_name = periph.hdl_prefix.."_wbgen2_pkg";
emit("package "..pkg_name.." is")
indent_right();
- emit("");
-
emit("");
emit("-- Input registers (user design -> WB slave)");
emit("");
-
+
cgen_vhdl_port_struct("in");
emit("");
@@ -83,51 +87,72 @@ function cgen_vhdl_package()
emit("");
cgen_vhdl_port_struct("out");
-
-
- indent_left();
+ emit("");
+ emit("-- functions");
+ emit("");
local typename = "t_"..periph.hdl_prefix.."_in_registers";
emit("function \"or\" (left, right: "..typename..") return "..typename..";");
emit("function f_x_to_zero (x:std_logic) return std_logic;");
emit("function f_x_to_zero (x:std_logic_vector) return std_logic_vector;");
+ emit("");
indent_left();
- indent_left();
emit("end package;");
emit("");
emit("package body "..pkg_name.." is");
+ indent_right();
+ emit("");
emit("function f_x_to_zero (x:std_logic) return std_logic is");
emit("begin")
+ indent_right();
emit("if x = '1' then")
+ indent_right();
emit("return '1';")
+ indent_left();
emit("else")
+ indent_right();
emit("return '0';")
+ indent_left();
emit("end if;")
+ indent_left();
emit("end function;");
+ emit("");
emit("function f_x_to_zero (x:std_logic_vector) return std_logic_vector is");
+ indent_right();
emit("variable tmp: std_logic_vector(x'length-1 downto 0);");
+ indent_left();
emit("begin");
+ indent_right();
emit("for i in 0 to x'length-1 loop");
+ indent_right();
emit("if(x(i) = 'X' or x(i) = 'U') then");
+ indent_right();
emit("tmp(i):= '0';");
+ indent_left();
emit("else");
+ indent_right();
emit("tmp(i):=x(i);");
+ indent_left();
emit("end if; ");
+ indent_left();
emit("end loop; ");
emit("return tmp;");
+ indent_left();
emit("end function;");
-
-
+ emit("");
emit("function \"or\" (left, right: "..typename..") return "..typename.." is");
+ indent_right();
emit("variable tmp: "..typename..";");
+ indent_left();
emit("begin");
+ indent_right();
for i=1,table.getn(g_portlist) do
local port = g_portlist[i];
@@ -137,8 +162,11 @@ function cgen_vhdl_package()
end
end
emit("return tmp;");
+ indent_left();
emit("end function;");
+ emit("");
+ indent_left();
emit("end package body;");
end
@@ -189,6 +217,7 @@ function cgen_vhdl_port_struct(direction)
emit(line);
end
emit(");");
+ indent_left();
end
--
2.8.1.windows.1
hdl/ip_cores/wishbone-gen_patches/0004-added-missing-function-for-type-un-signed.patch deleted 100644 → 0
View file @ 0ca74d29
From c68298349ed1c3ede781af609a073911160160bb Mon Sep 17 00:00:00 2001
From: Jan Pospisil <j.pospisil@cern.ch>
Date: Wed, 24 Aug 2016 19:13:11 +0200
Subject: [PATCH 4/7] added missing function for type (un)signed
---
cgen_vhdl.lua | 21 ++++++++++++++++++++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/cgen_vhdl.lua b/cgen_vhdl.lua
index 1bafa9b..6d50d1b 100644
--- a/cgen_vhdl.lua
+++ b/cgen_vhdl.lua
@@ -12,6 +12,7 @@
-- Modifications:
-- 2016-08-24: by Jan Pospisil (j.pospisil@cern.ch)
-- * better indent for VHDL package
+-- * added missing function for type (un)signed
--------------------------------------------------------------------------------
-- conversion table between VHDL data types and wbgen2 internal data types
@@ -94,9 +95,11 @@ function cgen_vhdl_package()
local typename = "t_"..periph.hdl_prefix.."_in_registers";
- emit("function \"or\" (left, right: "..typename..") return "..typename..";");
emit("function f_x_to_zero (x:std_logic) return std_logic;");
emit("function f_x_to_zero (x:std_logic_vector) return std_logic_vector;");
+ emit("function f_x_to_zero (x:signed) return signed;");
+ emit("function f_x_to_zero (x:unsigned) return unsigned;");
+ emit("function \"or\" (left, right: "..typename..") return "..typename..";");
emit("");
indent_left();
@@ -147,6 +150,22 @@ function cgen_vhdl_package()
emit("end function;");
emit("");
+ emit("function f_x_to_zero (x:signed) return signed is");
+ emit("begin");
+ indent_right();
+ emit("return signed(f_x_to_zero(std_logic_vector(x)));");
+ indent_left();
+ emit("end function;");
+ emit("");
+
+ emit("function f_x_to_zero (x:unsigned) return unsigned is");
+ emit("begin");
+ indent_right();
+ emit("return unsigned(f_x_to_zero(std_logic_vector(x)));");
+ indent_left();
+ emit("end function;");
+ emit("");
+
emit("function \"or\" (left, right: "..typename..") return "..typename.." is");
indent_right();
emit("variable tmp: "..typename..";");
--
2.8.1.windows.1
hdl/ip_cores/wishbone-gen_patches/0005-commented-out-debug-output.patch deleted 100644 → 0
View file @ 0ca74d29
From 8223570a84001abf102936a46d975ccc8d2c469d Mon Sep 17 00:00:00 2001
From: Jan Pospisil <j.pospisil@cern.ch>
Date: Wed, 24 Aug 2016 19:21:19 +0200
Subject: [PATCH 5/7] commented out debug output
---
wbgen_common.lua | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/wbgen_common.lua b/wbgen_common.lua
index 68e0190..9a34596 100644
--- a/wbgen_common.lua
+++ b/wbgen_common.lua
@@ -200,9 +200,9 @@ function align(field, offset)
newofs = a * math.floor((offset + a - 1) / a);
end
--- calculate the aligned offset
+ -- calculate the aligned offset
- print("Align ", field.name, field.align, offset, newofs);
+ -- print("Align ", field.name, field.align, offset, newofs);
return newofs;
end
--
2.8.1.windows.1
hdl/ip_cores/wishbone-gen_patches/0006-prettier-VHDL-output-rddata_reg-31-downto-8-others-X.patch deleted 100644 → 0
View file @ 0ca74d29
From 7e2536fa48aa59724b76c3e50776f864746a6297 Mon Sep 17 00:00:00 2001
From: Jan Pospisil <j.pospisil@cern.ch>
Date: Wed, 24 Aug 2016 20:15:19 +0200
Subject: [PATCH 6/7] prettier VHDL output ("rddata_reg(31 downto 8) <= (others
=> 'X');" instead of 24 individual lines)
---
wbgen_regbank.lua | 87 ++++++++++++++++++++++++++++++++++++++-----------------
1 file changed, 60 insertions(+), 27 deletions(-)
diff --git a/wbgen_regbank.lua b/wbgen_regbank.lua
index 230d441..96eea9d 100644
--- a/wbgen_regbank.lua
+++ b/wbgen_regbank.lua
@@ -5,6 +5,14 @@
-- CERN BE-Co-HT
-- LICENSED UNDER GPL v2
+--------------------------------------------------------------------------------
+-- Modifications:
+-- 2016-08-24: by Jan Pospisil (j.pospisil@cern.ch)
+-- * prettier VHDL output
+-- "rddata_reg(31 downto 8) <= (others => 'X');" instead of
+-- 24 individual lines
+--------------------------------------------------------------------------------
+
function gen_hdl_field_prefix(field, reg)
local field_count;
@@ -650,34 +658,59 @@ end
-- generates code which loads data unused bits of data output register with Xs
function fill_unused_bits(target, reg)
- local t={};
- local code={};
- local all_wo = true;
-
- foreach_subfield(reg, function(field, reg)
- if(field.type == SLV or field.type == SIGNED or field.type == UNSIGNED or field.type == CONSTANT) then
- for i=field.offset, (field.offset+field.size-1) do t[i] = 1; end
- elseif(field.type == BIT or field.type == MONOSTABLE) then
- t[field.offset] = 1;
- end
-
- if(field.access_bus ~= WRITE_ONLY) then all_wo = false; end
- end);
-
- if(all_wo) then
- for i = 0, DATA_BUS_WIDTH-1 do
- table_join(code, { va(vi(target, i), vundefined()); });
- end
- return code;
- end
+ local t={};
+ local code={};
+ local all_wo = true;
+
+ foreach_subfield(
+ reg,
+ function(field, reg)
+ if(field.type == SLV or field.type == SIGNED or field.type == UNSIGNED or field.type == CONSTANT) then
+ for i=field.offset, (field.offset+field.size-1) do
+ t[i] = 1;
+ end
+ elseif(field.type == BIT or field.type == MONOSTABLE) then
+ t[field.offset] = 1;
+ end
+
+ if(field.access_bus ~= WRITE_ONLY) then
+ all_wo = false;
+ end
+ end
+ );
+
+ function fill_unused_bits_range(target, from, to)
+ if(from == to) then
+ table_join(code, { va(vi(target, from), vundefined()); });
+ else
+ table_join(code, { va(vi(target, to, from), vothers('X')); });
+ end
+ end
- for i = 0, DATA_BUS_WIDTH-1 do
- if(t[i] == nil) then
- table_join(code, { va(vi(target, i), vundefined()); });
- end
- end
-
- return code;
+ if(all_wo) then
+ fill_unused_bits_range(target, 0, DATA_BUS_WIDTH-1);
+ return code;
+ end
+
+ range_start = nil;
+ for i = 0, DATA_BUS_WIDTH-1 do
+ if(t[i] == nil) then
+ if(range_start == nil) then
+ range_start = i;
+ end
+ else -- t[i] ~= nil
+ if(range_start ~= nil) then
+ fill_unused_bits_range(target, range_start, i-1);
+ range_start = nil;
+ end
+ end
+ end
+ if(range_start ~= nil) then
+ fill_unused_bits_range(target, range_start, DATA_BUS_WIDTH-1);
+ range_start = nil;
+ end
+
+ return code;
end
--
2.8.1.windows.1
hdl/ip_cores/wishbone-gen_patches/0007-added-functions-print_table-and-table_size-disable-c.patch deleted 100644 → 0
View file @ 0ca74d29
From 91af40398c34cc8c2afe9869404199116b401470 Mon Sep 17 00:00:00 2001
From: Jan Pospisil <j.pospisil@cern.ch>
Date: Thu, 25 Aug 2016 14:32:16 +0200
Subject: [PATCH 7/7] added functions print_table and table_size; disable
comment output for no extra code (field.extra_code seems to always be a
table)
---
target_pipelined_wb.lua | 10 ++++++++--
wbgen_common.lua | 28 ++++++++++++++++++++++++++++
2 files changed, 36 insertions(+), 2 deletions(-)
diff --git a/target_pipelined_wb.lua b/target_pipelined_wb.lua
index 2dcabfa..899a7f1 100644
--- a/target_pipelined_wb.lua
+++ b/target_pipelined_wb.lua
@@ -1,5 +1,11 @@
-- -*- Mode: LUA; tab-width: 2 -*-
+--------------------------------------------------------------------------------
+-- Modifications:
+-- 2016-08-25: by Jan Pospisil (j.pospisil@cern.ch)
+-- * disable comment output for no extra code (field.extra_code seems
+-- to always be a table)
+--------------------------------------------------------------------------------
MAX_ACK_LENGTH = 10;
@@ -282,9 +288,9 @@ function gen_bus_logic_pipelined_wb(mode)
foreach_subfield(reg,
function(field, reg)
- if (field.extra_code ~= nil) then
+ if (field.extra_code ~= nil and table_size(field.extra_code) > 0) then
table_join(ex_code, {vcomment(field.name); field.extra_code});
- end
+ end
end );
if(reg.optional == nil) then
diff --git a/wbgen_common.lua b/wbgen_common.lua
index 9a34596..e8f320f 100644
--- a/wbgen_common.lua
+++ b/wbgen_common.lua
@@ -1,5 +1,11 @@
-- -*- Mode: LUA; tab-width: 2 -*-
+--------------------------------------------------------------------------------
+-- Modifications:
+-- 2016-08-25: by Jan Pospisil (j.pospisil@cern.ch)
+-- * added functions print_table and table_size
+--------------------------------------------------------------------------------
+
-- some constants --
-- DEBUG MACROS
@@ -558,3 +564,25 @@ function deepcopy(object)
end
return _copy(object)
end
+
+function print_table(t, level)
+ level = level or 0
+ local indent = ""
+ for i = 1,level do indent=indent.." "; end
+ for k,v in pairs(t) do
+ if (type(v)=="table") then
+ print(indent..k..", "..type(v)..", "..table_size(v));
+ print_table(v, level+1);
+ else
+ print(indent..k..", "..type(v)..", "..tostring(v));
+ end
+ end
+end
+
+function table_size(t)
+ local size = 0
+ for k,v in pairs(t) do
+ size = size + 1
+ end
+ return size
+end
--
2.8.1.windows.1
wr-cores @ 63d6e85c
Subproject commit 63d6e85c292e57360fe106acfd08de66d3c0acb7
hdl/svec/rtl/HeartBeat.vhd deleted 100644 → 0
View file @ 0ca74d29
-------------------------------------------------------------------------------
-- Title : Heart beat generator
-- Project : FMC DEL 1ns 2cha (FFPG)
-- URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
-------------------------------------------------------------------------------
-- File : HeartBeat.vhd
-- Author(s) : Jan Pospisil <j.pospisil@cern.ch>
-- Company : CERN (BE-BI-QP)
-- Created : 2016-07-28
-- Last update: 2016-08-24
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Generates "glowing" signal, intended for LED signalization.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CERN (BE-BI-QP)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2016-08-24 1.0 Jan Pospisil
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity HeartBeat is
generic (
g_ClkFrequency: positive -- input clock frequency in Hz
);
port (
Clk_ik: in std_logic;
Reset_ir: in std_logic;
HeartBeat_o: out std_logic := '0'
);
end entity;
architecture syn of HeartBeat is
--! computes least possible width of the vector to store value X
-- http://stackoverflow.com/a/12751341/615627
function f_log2(x: natural) return natural is
variable i: natural;
begin
i := 0;
while (2**i < x) loop
i := i + 1;
end loop;
return i;
end function;
function f_min(a, b: integer) return integer is
begin
if a < b then
return a;
else
return b;
end if;
end function;
function f_max(a, b: integer) return integer is
begin
if a > b then
return a;
else
return b;
end if;
end function;
constant c_ClkFreqWidth: positive := f_log2(g_ClkFrequency);
constant c_PwmWidth: positive := f_max(f_min(c_ClkFreqWidth, 12), 4);
constant c_DividerWidth: natural := c_ClkFreqWidth - c_PwmWidth;
constant c_DividerLimit: natural := g_ClkFrequency / (2**c_PwmWidth);
signal PwmCountDown: std_logic := '0';
signal UpdatePwmValue, PwmCounterOverflow: std_logic;
signal PwmCounter_b, PwmValue_b, PwmValue_bd: signed(c_PwmWidth-1 downto 0) := (others => '0');
begin
gNeedDivider: if c_DividerWidth > 0 generate
cDivider: entity work.Counter(syn)
generic map (
g_Width => c_DividerWidth,
g_Limit => c_DividerLimit
)
port map (
Clk_ik => Clk_ik,
Reset_ir => Reset_ir,
Enable_i => '1',
Set_i => '0',
SetValue_ib => (others => '0'),
Overflow_o => UpdatePwmValue,
Value_ob => open
);
end generate;
gDoesntNeedDivider: if c_DividerWidth = 0 generate
UpdatePwmValue <= '1';
end generate;
pPwmValue: process (Clk_ik) begin
if rising_edge(Clk_ik) then
if Reset_ir = '1' then
PwmValue_b <= (others => '0');
PwmCountDown <= '0';
elsif UpdatePwmValue = '1' then
if PwmCountDown = '1' then
if PwmValue_b = to_signed(1, c_PwmWidth) then
PwmCountDown <= '0';
PwmValue_b <= PwmValue_b + 1;
else
PwmValue_b <= PwmValue_b - 1;
end if;
else
if PwmValue_b = to_signed(-1, c_PwmWidth) then
PwmCountDown <= '1';
PwmValue_b <= PwmValue_b - 1;
else
PwmValue_b <= PwmValue_b + 1;
end if;
end if;
end if;
end if;
end process;
cPwmCounter: entity work.Counter(syn)
generic map (
g_Width => c_PwmWidth
)
port map (
Clk_ik => Clk_ik,
Reset_ir => Reset_ir,
Enable_i => '1',
Set_i => '0',
SetValue_ib => (others => '0'),
Overflow_o => PwmCounterOverflow,
signed(Value_ob) => PwmCounter_b
);
pPwmValueReg: process (Clk_ik) is begin
if rising_edge(Clk_ik) then
if PwmCounterOverflow = '1' then
PwmValue_bd <= PwmValue_b;
end if;
end if;
end process;
pHearBeat: process (Clk_ik) begin
if rising_edge(Clk_ik) then
if Reset_ir = '1' then
HeartBeat_o <= '0';
else
if PwmCounter_b = 0 then
HeartBeat_o <= '1';
end if;
if PwmCounter_b = PwmValue_bd then
HeartBeat_o <= '0';
end if;
end if;
end if;
end process;
end architecture;
hdl/svec/rtl/HeartBeat_tb.vhd deleted 100644 → 0
View file @ 0ca74d29
-------------------------------------------------------------------------------
-- Title : Testbench for HeartBeat.vhd
-- Project : FMC DEL 1ns 2cha (FFPG)
-- URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
-------------------------------------------------------------------------------
-- File : HeartBeat_tb.vhd
-- Author(s) : Jan Pospisil <j.pospisil@cern.ch>
-- Company : CERN (BE-BI-QP)
-- Created : 2016-07-28
-- Last update: 2016-08-24
-- Standard : VHDL2008
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CERN (BE-BI-QP)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2016-08-24 1.0 Jan Pospisil
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity HeartBeat_tb is
end entity;
architecture testbench of HeartBeat_tb is
constant c_ClkFrequency: positive := 300_000;
constant c_ClkPeriod: time := (1 sec)/real(c_ClkFrequency);
procedure f_Tick(ticks: in natural) is begin
wait for ticks * c_ClkPeriod;
end procedure;
signal Clk_ik, Reset_ir, HeartBeat_o: std_logic;
signal HeartBeatPwmValue: time := 0 ns;
begin
cDUT: entity work.HeartBeat(syn)
generic map (
g_ClkFrequency => c_ClkFrequency
)
port map (
Clk_ik,
Reset_ir,
HeartBeat_o
);
pClk: process is begin
Clk_ik <= '0';
wait for c_ClkPeriod/2;
Clk_ik <= '1';
wait for c_ClkPeriod/2;
end process;
pTest: process is begin
Reset_ir <= '1';
f_Tick(5);
Reset_ir <= '0';
f_Tick(1e6);
assert false report "NONE. End of simulation." severity failure;
wait;
end process pTest;
pRC: process (HeartBeat_o) is
variable LastOn: time := 0 ns;
begin
if rising_edge(HeartBeat_o) then
LastOn := now;
else
HeartBeatPwmValue <= now - LastOn;
end if;
end process;
end architecture;
hdl/svec/rtl/SvecTopFfpg.vhd deleted 100644 → 0
View file @ 0ca74d29
-------------------------------------------------------------------------------
-- Title : Top-level entity for implementation on SVEC carrier card
-- Project : FMC DEL 1ns 2cha (FFPG)
-- URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
-------------------------------------------------------------------------------
-- File : SvecTopFfpg.vhd
-- Author(s) : Jan Pospisil <j.pospisil@cern.ch>
-- Company : CERN (BE-BI-QP)
-- Created : 2016-07-26
-- Last update: 2016-08-24
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Contains code for two FMC mezzanines, communication via VME bus
-- and other board specific code.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CERN (BE-BI-QP)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2016-08-24 1.0 Jan Pospisil
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.wishbone_pkg.all;
use work.gencores_pkg.all;
use work.FfpgPkg.all;
entity SvecTopFfpg is
port (
-- Local 20MHz VCXO oscillator
Clk20_ik: in std_logic;
-- Reset from system FPGA
Reset_inr: in std_logic;
-- DAC interface (20MHz and 25MHz VCXO)
Pll20DacDin_o: out std_logic;
Pll20DacSclk_o: out std_logic;
Pll20DacSync_on: out std_logic;
Pll25DacDin_o: out std_logic;
Pll25DacSclk_o: out std_logic;
Pll25DacSync_on: out std_logic;
-- Carrier font panel LEDs & LEMOs
FpLedsLineEnable_ob2: out std_logic_vector(1 downto 0);
FpLedsLine_ob2: out std_logic_vector(1 downto 0);
FpLedsColumn_ob4: out std_logic_vector(3 downto 0);
FpLemo_ob4: out std_logic_vector(4 downto 1);
FpLemoDir1_A2B_o: out std_logic;
FpLemoDir2_A2B_o: out std_logic;
FpLemoDir34_A2B_o: out std_logic;
FpLemoTerm_oeb4: out std_logic_vector(4 downto 1);
-- Carrier I2C EEPROM
CarrierScl_io: inout std_logic;
CarrierSda_io: inout std_logic;
-- PCB revision
PcbRev_i: in std_logic_vector(4 downto 0);
-- Carrier 1-wire interface (DS18B20 thermometer + unique ID)
CarrierOneWire_io: inout std_logic;
------------------------------------------
-- VME interface
------------------------------------------
VmeWrite_n_i : in std_logic;
VmeSysreset_n_i : in std_logic;
--VmeSysclk_i : in std_logic;
VmeRetry_oe_o : out std_logic;
VmeRetry_n_o : out std_logic;
VmeLword_n_b : inout std_logic;
VmeIackout_n_o : out std_logic;
VmeIackin_n_i : in std_logic;
VmeIack_n_i : in std_logic;
--VmeGap_i : in std_logic;
VmeDtack_oe_o : out std_logic;
VmeDtack_n_o : out std_logic;
VmeDs_n_i : in std_logic_vector(1 downto 0);
VmeData_oe_n_o : out std_logic;
VmeData_dir_o : out std_logic;
VmeBerr_o : out std_logic;
VmeAs_n_i : in std_logic;
VmeAddr_oe_n_o : out std_logic;
VmeAddr_dir_o : out std_logic;
VmeIrq_n_o : out std_logic_vector(7 downto 1);
VmeGa_i : in std_logic_vector(5 downto 0);
VmeData_b : inout std_logic_vector(31 downto 0);
VmeAm_i : in std_logic_vector(5 downto 0);
VmeAddr_b : inout std_logic_vector(31 downto 1);
------------------------------------------
-- FMC slot management
------------------------------------------
Fmc0Present_in: in std_logic; -- Mezzanine present (active low)
-- Fmc0Scl: inout std_logic; -- Mezzanine system I2C clock (EEPROM)
-- Fmc0Sda: inout std_logic; -- Mezzanine system I2C data (EEPROM)
Fmc1Present_in: in std_logic; -- Mezzanine present (active low)
-- Fmc1Scl: inout std_logic; -- Mezzanine system I2C clock (EEPROM)
-- Fmc1Sda: inout std_logic; -- Mezzanine system I2C data (EEPROM)
------------------------------------------
-- FMC slot 0
------------------------------------------
-- clock
Fmc0ClkIn0P_ik: in std_logic;
Fmc0ClkIn0N_ik: in std_logic;
-- DACs
Fmc0TriggerDac_o: out t_Ad5600Interface;
Fmc0VcxoDac_o: out t_Ad5600Interface;
-- output enable
Fmc0Ch1OutputEnable_o: out std_logic;
Fmc0Ch2OutputEnable_o: out std_logic;
-- signal feedback
Fmc0Ch1OutCal_i: in std_logic;
Fmc0Ch2OutCal_i: in std_logic;
-- delay configuration
Fmc0DelayValue_ob: out unsigned(9 downto 0);
Fmc0Ch1SetLe_on: out std_logic;
Fmc0Ch1ResLe_on: out std_logic;
Fmc0Ch2SetLe_on: out std_logic;
Fmc0Ch2ResLe_on: out std_logic;
Fmc0Ch1SetP_o: out std_logic;
Fmc0Ch1SetN_o: out std_logic;
Fmc0Ch1ResP_o: out std_logic;
Fmc0Ch1ResN_o: out std_logic;
Fmc0Ch2SetP_o: out std_logic;
Fmc0Ch2SetN_o: out std_logic;
Fmc0Ch2ResP_o: out std_logic;
Fmc0Ch2ResN_o: out std_logic;
Fmc0TriggerP_i: in std_logic;
Fmc0TriggerN_i: in std_logic;
-- AD9512 SPI
Fmc0SpiAd9512Sclk_o: out std_logic;
Fmc0SpiAd9512Mosi_o: out std_logic;
Fmc0SpiAd9512Miso_i: in std_logic;
Fmc0SpiAd9512Cs_on: out std_logic;
-- AD9512 func. pin
Fmc0Ad9512Func_o: out std_logic;
-- clock selection pin of SY58017U
Fmc0Clk2Sel_o: out std_logic;
-- clock output
Fmc0ClkOutP_ok: out std_logic;
Fmc0ClkOutN_ok: out std_logic;
-- temperature chip interface
Fmc0Onewire_io: inout std_logic;
-- LEDs
Fmc0Led_ob: out std_logic_vector(4 downto 1);
------------------------------------------
-- FMC slot 1
------------------------------------------
-- clock
Fmc1ClkIn0P_ik: in std_logic;
Fmc1ClkIn0N_ik: in std_logic;
-- DACs
Fmc1TriggerDac_o: out t_Ad5600Interface;
Fmc1VcxoDac_o: out t_Ad5600Interface;
-- output enable
Fmc1Ch1OutputEnable_o: out std_logic;
Fmc1Ch2OutputEnable_o: out std_logic;
-- signal feedback
Fmc1Ch1OutCal_i: in std_logic;
Fmc1Ch2OutCal_i: in std_logic;
-- delay configuration
Fmc1DelayValue_ob: out unsigned(9 downto 0);
Fmc1Ch1SetLe_on: out std_logic;
Fmc1Ch1ResLe_on: out std_logic;
Fmc1Ch2SetLe_on: out std_logic;
Fmc1Ch2ResLe_on: out std_logic;
Fmc1Ch1SetP_o: out std_logic;
Fmc1Ch1SetN_o: out std_logic;
Fmc1Ch1ResP_o: out std_logic;
Fmc1Ch1ResN_o: out std_logic;
Fmc1Ch2SetP_o: out std_logic;
Fmc1Ch2SetN_o: out std_logic;
Fmc1Ch2ResP_o: out std_logic;
Fmc1Ch2ResN_o: out std_logic;
Fmc1TriggerP_i: in std_logic;
Fmc1TriggerN_i: in std_logic;
-- AD9512 SPI
Fmc1SpiAd9512Sclk_o: out std_logic;
Fmc1SpiAd9512Mosi_o: out std_logic;
Fmc1SpiAd9512Miso_i: in std_logic;
Fmc1SpiAd9512Cs_on: out std_logic;
-- AD9512 func. pin
Fmc1Ad9512Func_o: out std_logic;
-- clock selection pin of SY58017U
Fmc1Clk2Sel_o: out std_logic;
-- clock output
Fmc1ClkOutP_ok: out std_logic;
Fmc1ClkOutN_ok: out std_logic;
-- temperature chip interface
Fmc1Onewire_io: inout std_logic;
-- LEDs
Fmc1Led_ob: out std_logic_vector(4 downto 1)
);
end entity;
architecture rtl of SvecTopFfpg is
type t_PllSettings is record
InputFrequency: integer; -- in Hz
Divide: integer;
Mult: integer;
RefJitter: real;
end record;
function f_ComputePllDivider(PllSettings: t_PllSettings; OutputFrequency: integer) return integer is
variable VcoFrequency, Result: integer;
begin
assert PllSettings.InputFrequency * PllSettings.Mult rem PllSettings.Divide = 0
report "Cannot set the PLL - VCO frequency is not an integer!"
severity failure;
VcoFrequency := PllSettings.InputFrequency * PllSettings.Mult / PllSettings.Divide;
assert VcoFrequency rem OutputFrequency = 0
report "Cannot set the output frequency to "&integer'image(OutputFrequency)&" Hz - PLL DIVIDE is not an integer!"
severity failure;
Result := VcoFrequency / OutputFrequency;
return Result;
end function;
constant c_PllSettings: t_PllSettings := (
InputFrequency => 20_000_000,
Divide => 1,
Mult => 50,
RefJitter => 0.016
);
constant c_ClkSysFrequency: positive := 62_500_000; -- in Hz
-- SVEC carrier CSR constants
constant c_CarrierType: std_logic_vector(15 downto 0) := X"0002";
-- Number of slave port(s) on the wishbone crossbar
constant c_NumWbMasters: integer := 1;
-- Number of master port(s) on the wishbone crossbar
constant c_NumWbSlaves: integer := 5;
-- Wishbone master(s)
constant c_MasterVmeId: integer := 0;
-- Wishbone slave(s)
constant c_SlaveEepromId: integer := 0;
constant c_SlaveOnewireId: integer := 1;
constant c_SlaveCsrId: integer := 2;
constant c_SlaveFmc0Id: integer := 3;
constant c_SlaveFmc1Id: integer := 4;
-- Top module repository url
constant c_SdbRepoUrl: t_sdb_repo_url := (
repo_url => "git://ohwr.org/fmc-projects/fmc-del-1ns-2cha.git ");
-- sdb header address
constant c_SdbAddress: t_wishbone_address := x"0000_0000";
constant c_SvecCsrSdb: t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000001F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00006603",
version => x"00000001",
date => x"20121116",
name => "WB-SVEC-CSR ")));
-- Wishbone crossbar layout
constant c_InterconnectLayout: t_sdb_record_array(c_NumWbSlaves-1+1 downto 0) := (
0 => f_sdb_embed_device(c_xwb_i2c_master_sdb, x"0000_1000"),
1 => f_sdb_embed_device(c_xwb_onewire_master_sdb, x"0000_1100"),
2 => f_sdb_embed_device(c_SvecCsrSdb, x"0000_1200"),
3 => f_sdb_embed_bridge(c_FfpgBridgeSdb, x"0002_0000"),
4 => f_sdb_embed_bridge(c_FfpgBridgeSdb, x"0006_0000"),
5 => f_sdb_embed_repo_url(c_SdbRepoUrl)
);
-- !! maximum addressable VME space on SVEC card is x"0008_0000" !!
signal Clk20Buffered_k: std_logic;
signal PllLocked, PllFeedback: std_logic;
signal ClkSysUnbuffered_k, ClkSys_k: std_logic;
signal PowerupResetCounter: unsigned(7 downto 0) := (others => '0');
signal ResetSys_r: std_logic := '1';
signal ResetSys_nr: std_logic;
signal SwResetFmc0_r: std_logic := '0';
signal SwResetFmc0Out_n, SwResetFmc0In_n, SwResetFmc0Load: std_logic;
signal Fmc0Reset_r: std_logic;
signal SwResetFmc1_r: std_logic := '0';
signal SwResetFmc1Out_n, SwResetFmc1In_n, SwResetFmc1Load: std_logic;
signal Fmc1Reset_r: std_logic;
signal VmeAddr_b_out: std_logic_vector(31 downto 1);
signal VmeAddr_dir_int: std_logic;
signal VmeData_b_out: std_logic_vector(31 downto 0);
signal VmeData_dir_int: std_logic;
signal VmeLword_n_b_out: std_logic;
-- Wishbone buse(s) from crossbar master port(s)
signal CnxMasterOut: t_wishbone_master_out_array(c_NumWbSlaves-1 downto 0);
signal CnxMasterIn: t_wishbone_master_in_array(c_NumWbSlaves-1 downto 0);
-- Wishbone buse(s) to crossbar slave port(s)
signal CnxSlaveOut: t_wishbone_slave_out_array(c_NumWbMasters-1 downto 0);
signal CnxSlaveIn: t_wishbone_slave_in_array(c_NumWbMasters-1 downto 0);
signal CarrierOwr, CarrierOwrEn: std_logic;
signal CarrierSclIn, CarrierSclOe_n, CarrierSclOut: std_logic;
signal CarrierSdaIn, CarrierSdaOe_n, CarrierSdaOut: std_logic;
signal HeartBeat: std_logic;
signal LedState: std_logic_vector(15 downto 0);
signal VmeAccess: std_logic;
-- for differential inputs
signal Fmc0ClkIn0_k, Fmc0Trigger: std_logic;
signal Fmc1ClkIn0_k, Fmc1Trigger: std_logic;
-- for differentials outputs
signal Fmc0Ch1Set, Fmc0Ch1Res, Fmc0Ch2Set, Fmc0Ch2Res: std_logic;
signal Fmc0ClkOutDdr, Fmc0ClkOut_k: std_logic;
signal Fmc1Ch1Set, Fmc1Ch1Res, Fmc1Ch2Set, Fmc1Ch2Res: std_logic;
signal Fmc1ClkOutDdr, Fmc1ClkOut_k: std_logic;
begin
------------------------------------------------------------------------------
-- Clock distribution
------------------------------------------------------------------------------
-- AD5662BRMZ-1 DAC output powers up to 0V. The output remains valid until a
-- write sequence arrives to the DAC.
-- To avoid spurious writes, the DAC interface outputs are fixed to safe values.
Pll20DacDin_o <= '0';
Pll20DacSclk_o <= '0';
Pll20DacSync_on <= '1';
Pll25DacDin_o <= '0';
Pll25DacSclk_o <= '0';
Pll25DacSync_on <= '1';
cClk20Buf: IBUFG
port map (
I => Clk20_ik,
O => Clk20Buffered_k
);
cPll: PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => c_PllSettings.Divide,
CLKFBOUT_MULT => c_PllSettings.Mult,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => f_ComputePllDivider(c_PllSettings, c_ClkSysFrequency),
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => (1.0)/real(c_PllSettings.InputFrequency)*1.0e9, -- in ns
REF_JITTER => c_PllSettings.RefJitter
)
port map (
CLKFBOUT => PllFeedback,
CLKOUT0 => ClkSysUnbuffered_k,
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => PllLocked,
RST => '0',
CLKFBIN => PllFeedback,
CLKIN => Clk20Buffered_k
);
cClkSysBuf: BUFG
port map (
I => ClkSysUnbuffered_k,
O => ClkSys_k
);
------------------------------------------------------------------------------
-- System reset
------------------------------------------------------------------------------
pPowerupReset: process (ClkSys_k) begin
if rising_edge(ClkSys_k) then
if (VmeSysreset_n_i = '0' or Reset_inr = '0') then
ResetSys_r <= '1';
elsif PllLocked = '1' then
if PowerupResetCounter = "11111111" then
ResetSys_r <= '0';
else
ResetSys_r <= '1';
PowerupResetCounter <= PowerupResetCounter + 1;
end if;
else
ResetSys_r <= '1';
PowerupResetCounter <= (others => '0');
end if;
end if;
end process;
ResetSys_nr <= not ResetSys_r;
------------------------------------------------------------------------------
-- VME interface
------------------------------------------------------------------------------
cVmeCore: entity work.xvme64x_core(wrapper)
port map (
clk_i => ClkSys_k,
rst_n_i => ResetSys_nr,
VME_AS_n_i => VmeAs_n_i,
VME_RST_n_i => VmeSysreset_n_i,
VME_WRITE_n_i => VmeWrite_n_i,
VME_AM_i => VmeAm_i,
VME_DS_n_i => VmeDs_n_i,
VME_GA_i => VmeGa_i,
VME_BERR_o => VmeBerr_o,
VME_DTACK_n_o => VmeDtack_n_o,
VME_RETRY_n_o => VmeRetry_n_o,
VME_RETRY_OE_o => VmeRetry_oe_o,
VME_LWORD_n_b_i => VmeLword_n_b,
VME_LWORD_n_b_o => VmeLword_n_b_out,
VME_ADDR_b_i => VmeAddr_b,
VME_DATA_b_o => VmeData_b_out,
VME_ADDR_b_o => VmeAddr_b_out,
VME_DATA_b_i => VmeData_b,
VME_IRQ_n_o => VmeIrq_n_o,
VME_IACK_n_i => VmeIack_n_i,
VME_IACKIN_n_i => VmeIackin_n_i,
VME_IACKOUT_n_o => VmeIackout_n_o,
VME_DTACK_OE_o => VmeDtack_oe_o,
VME_DATA_DIR_o => VmeData_dir_int,
VME_DATA_OE_N_o => VmeData_oe_n_o,
VME_ADDR_DIR_o => VmeAddr_dir_int,
VME_ADDR_OE_N_o => VmeAddr_oe_n_o,
master_o => CnxSlaveIn(c_MasterVmeId),
master_i => CnxSlaveOut(c_MasterVmeId),
irq_i => '0'
);
-- VME tri-state buffers
VmeData_b <=
VmeData_b_out when VmeData_dir_int = '1' else
(others => 'Z');
VmeAddr_b <=
VmeAddr_b_out when VmeAddr_dir_int = '1' else
(others => 'Z');
VmeLword_n_b <=
VmeLword_n_b_out when VmeAddr_dir_int = '1' else
'Z';
VmeAddr_dir_o <= VmeAddr_dir_int;
VmeData_dir_o <= VmeData_dir_int;
------------------------------------------------------------------------------
-- CSR wishbone crossbar
------------------------------------------------------------------------------
cWbSdbCrossbar: entity work.xwb_sdb_crossbar(rtl)
generic map (
g_num_masters => c_NumWbMasters,
g_num_slaves => c_NumWbSlaves,
g_registered => true,
g_wraparound => true,
g_layout => c_InterconnectLayout,
g_sdb_addr => c_SdbAddress
)
port map (
clk_sys_i => ClkSys_k,
rst_n_i => ResetSys_nr,
slave_i => CnxSlaveIn,
slave_o => CnxSlaveOut,
master_i => CnxMasterIn,
master_o => CnxMasterOut
);
------------------------------------------------------------------------------
-- I2C master
-- Carrier EEPROM
------------------------------------------------------------------------------
cCarrierI2c: entity work.xwb_i2c_master(rtl)
generic map (
g_interface_mode => CLASSIC,
g_address_granularity => BYTE,
g_num_interfaces => 1
)
port map (
clk_sys_i => ClkSys_k,
rst_n_i => ResetSys_nr,
slave_i => CnxMasterOut(c_SlaveEepromId),
slave_o => CnxMasterIn(c_SlaveEepromId),
desc_o => open,
scl_pad_i(0) => CarrierSclIn,
scl_pad_o(0) => CarrierSclOut,
scl_padoen_o(0) => CarrierSclOe_n,
sda_pad_i(0) => CarrierSdaIn,
sda_pad_o(0) => CarrierSdaOut,
sda_padoen_o(0) => CarrierSdaOe_n
);
-- Tri-state buffer for SDA and SCL
CarrierScl_io <=
CarrierSclOut when CarrierSclOe_n = '0' else
'Z';
CarrierSclIn <= CarrierScl_io;
CarrierSda_io <=
CarrierSdaOut when CarrierSdaOe_n = '0' else
'Z';
CarrierSdaIn <= CarrierSda_io;
------------------------------------------------------------------------------
-- Carrier 1-wire master
-- DS18B20 (thermometer + unique ID)
------------------------------------------------------------------------------
cCarrierOnewire: entity work.xwb_onewire_master(rtl)
generic map (
g_interface_mode => CLASSIC,
g_address_granularity => BYTE,
g_num_ports => 1,
g_ow_btp_normal => "5.0",
g_ow_btp_overdrive => "1.0",
g_CDR_N => (c_ClkSysFrequency/1e6)*5 - 1,
g_CDR_O => (c_ClkSysFrequency/1e6)*1 - 1
)
port map (
clk_sys_i => ClkSys_k,
rst_n_i => ResetSys_nr,
slave_i => CnxMasterOut(c_SlaveOnewireId),
slave_o => CnxMasterIn(c_SlaveOnewireId),
desc_o => open,
owr_pwren_o => open,
owr_en_o(0) => CarrierOwrEn,
owr_i(0) => CarrierOwr
);
CarrierOneWire_io <=
'0' when CarrierOwrEn = '1' else
'Z';
CarrierOwr <= CarrierOneWire_io;
------------------------------------------------------------------------------
-- Carrier CSR
-- Carrier type and PCB version
-- Carrier status (PLL, FMC presence)
------------------------------------------------------------------------------
cCarrierCsr: entity work.carrier_csr(syn)
port map (
rst_n_i => ResetSys_nr,
clk_sys_i => ClkSys_k,
wb_adr_i => CnxMasterOut(c_SlaveCsrId).adr(3 downto 2), -- CnxMasterOut.adr is byte address
wb_dat_i => CnxMasterOut(c_SlaveCsrId).dat,
wb_dat_o => CnxMasterIn(c_SlaveCsrId).dat,
wb_cyc_i => CnxMasterOut(c_SlaveCsrId).cyc,
wb_sel_i => CnxMasterOut(c_SlaveCsrId).sel,
wb_stb_i => CnxMasterOut(c_SlaveCsrId).stb,
wb_we_i => CnxMasterOut(c_SlaveCsrId).we,
wb_ack_o => CnxMasterIn(c_SlaveCsrId).ack,
wb_stall_o => CnxMasterIn(c_SlaveCsrId).stall,
carrier_csr_carrier_pcb_rev_i => PcbRev_i,
carrier_csr_carrier_reserved_i => (others => '0'),
carrier_csr_carrier_type_i => c_CarrierType,
carrier_csr_stat_fmc0_pres_i => Fmc0Present_in,
carrier_csr_stat_fmc1_pres_i => Fmc1Present_in,
carrier_csr_stat_sys_pll_lck_i => PllLocked,
carrier_csr_stat_ddr0_cal_done_i => '0', -- not implemented
carrier_csr_stat_ddr1_cal_done_i => '0', -- not implemented
carrier_csr_ctrl_fp_leds_man_o => open, -- not implemented
carrier_csr_rst_fmc0_n_o => SwResetFmc0Out_n,
carrier_csr_rst_fmc0_n_i => SwResetFmc0In_n,
carrier_csr_rst_fmc0_n_load_o => SwResetFmc0Load,
carrier_csr_rst_fmc1_n_o => SwResetFmc1Out_n,
carrier_csr_rst_fmc1_n_i => SwResetFmc1In_n,
carrier_csr_rst_fmc1_n_load_o => SwResetFmc1Load
);
-- Unused wishbone signals
CnxMasterIn(c_SlaveCsrId).err <= '0';
CnxMasterIn(c_SlaveCsrId).rty <= '0';
CnxMasterIn(c_SlaveCsrId).int <= '0';
-- external software reset registers (to assign a non-zero default value)
pSwResetFmc0: process (ClkSys_k) begin
if rising_edge(ClkSys_k) then
if ResetSys_r = '1' then
SwResetFmc0_r <= '0';
elsif SwResetFmc0Load = '1' then
SwResetFmc0_r <= not SwResetFmc0Out_n;
end if;
end if;
end process;
SwResetFmc0In_n <= not SwResetFmc0_r;
Fmc0Reset_r <= ResetSys_r or SwResetFmc0_r;
pSwResetFmc1: process (ClkSys_k) begin
if rising_edge(ClkSys_k) then
if ResetSys_r = '1' then
SwResetFmc1_r <= '0';
elsif SwResetFmc1Load = '1' then
SwResetFmc1_r <= not SwResetFmc1Out_n;
end if;
end if;
end process;
SwResetFmc1In_n <= not SwResetFmc1_r;
Fmc1Reset_r <= ResetSys_r or SwResetFmc1_r;
------------------------------------------------------------------------------
-- FPGA loaded led (heart beat)
------------------------------------------------------------------------------
cHeartBeat: entity work.HeartBeat(syn)
generic map (
g_ClkFrequency => c_ClkSysFrequency
)
port map (
Clk_ik => ClkSys_k,
Reset_ir => ResetSys_r,
HeartBeat_o => HeartBeat
);
------------------------------------------------------------------------------
-- Front panel LED control
------------------------------------------------------------------------------
cLedController: entity work.gc_bicolor_led_ctrl
generic map (
g_nb_column => 4,
g_nb_line => 2,
g_clk_freq => c_ClkSysFrequency, -- in Hz
g_refresh_rate => 250 -- in Hz
)
port map (
clk_i => ClkSys_k,
rst_n_i => ResetSys_nr,
led_intensity_i => "1100100", -- in %
led_state_i => LedState,
column_o => FpLedsColumn_ob4,
line_o => FpLedsLine_ob2,
line_oen_o => FpLedsLineEnable_ob2
);
cSlowToggle: entity work.SlowToggle(behavioral)
generic map (
g_Width => 1,
g_Ticks => c_ClkSysFrequency/15
)
port map (
Clk_ik => ClkSys_k,
Reset_ir => ResetSys_r,
Test_i => '0',
Signal_ib(0) => CnxSlaveIn(c_MasterVmeId).cyc,
Signal_ob(0) => VmeAccess
);
-- LED 1 : VME access
LedState(1 downto 0) <=
c_led_green when VmeAccess = '1' else
c_led_off;
-- LED 2 :
LedState(3 downto 2) <= c_led_red;
-- LED 3 :
LedState(5 downto 4) <= c_led_red_green;
-- LED 4 :
LedState(7 downto 6) <= '0' & HeartBeat;
-- LED 5 :
LedState(9 downto 8) <= c_led_off;
-- LED 6 :
LedState(11 downto 10) <= c_led_off;
-- LED 7 :
LedState(13 downto 12) <= c_led_off;
-- LED 8 :
LedState(15 downto 14) <= c_led_off;
------------------------------------------------------------------------------
-- FMC Slot 0 - FFPG
------------------------------------------------------------------------------
cFmc0ClkIn0Ibufgds: IBUFGDS
generic map (
DIFF_TERM => TRUE
)
port map (
I => Fmc0ClkIn0P_ik,
IB => Fmc0ClkIn0N_ik,
O => Fmc0ClkIn0_k
);
cFmc0TriggerIbufds: IBUFDS
generic map (
DIFF_TERM => TRUE
)
port map (
I => Fmc0TriggerP_i,
IB => Fmc0TriggerN_i,
O => Fmc0Trigger
);
cFmc0FfpgCore: entity work.FfpgCore(syn)
generic map (
g_ClkFrequency => c_ClkSysFrequency -- input clock frequency in Hz
)
port map (
-- Wishbone connection
Clk_ik => ClkSys_k,
Reset_ira => Fmc0Reset_r, -- synchronized locally for better timing
Wb_i => CnxMasterOut(c_SlaveFmc0Id),
Wb_o => CnxMasterIn(c_SlaveFmc0Id),
---- FMC interface
-- clock
ClkIn0_ik => Fmc0ClkIn0_k,
-- DACs
TriggerDac_o => Fmc0TriggerDac_o,
VcxoDac_o => Fmc0VcxoDac_o,
-- output enable
Ch1OutputEnable_o => Fmc0Ch1OutputEnable_o,
Ch2OutputEnable_o => Fmc0Ch2OutputEnable_o,
-- delay configuration
DelayValue_ob => Fmc0DelayValue_ob,
Ch1SetLe_on => Fmc0Ch1SetLe_on,
Ch1ResLe_on => Fmc0Ch1ResLe_on,
Ch2SetLe_on => Fmc0Ch2SetLe_on,
Ch2ResLe_on => Fmc0Ch2ResLe_on,
Ch1Set_o => Fmc0Ch1Set,
Ch1Res_o => Fmc0Ch1Res,
Ch2Set_o => Fmc0Ch2Set,
Ch2Res_o => Fmc0Ch2Res,
Trigger_i => Fmc0Trigger,
-- AD9512 SPI
SpiAd9512Sclk_o => Fmc0SpiAd9512Sclk_o,
SpiAd9512Mosi_o => Fmc0SpiAd9512Mosi_o,
SpiAd9512Miso_i => Fmc0SpiAd9512Miso_i,
SpiAd9512Cs_on => Fmc0SpiAd9512Cs_on,
-- AD9512 func. pin
Ad9512Func_o => Fmc0Ad9512Func_o,
-- clock selection pin of SY58017U
Clk2Sel_o => Fmc0Clk2Sel_o,
-- clock output
ClkOut_ok => Fmc0ClkOut_k,
-- temperature chip interface
Onewire_io => Fmc0Onewire_io,
-- LEDs
Led_ob => Fmc0Led_ob
);
-- feedback loop to FP LEMO
FpLemo_ob4(3) <= Fmc0Ch1OutCal_i;
FpLemo_ob4(4) <= Fmc0Ch2OutCal_i;
FpLemoDir34_A2B_o <= '1';
FpLemoTerm_oeb4(4 downto 3) <= "00";
cFmc0Ch1SetObufds: OBUFDS
port map (
I => Fmc0Ch1Set,
O => Fmc0Ch1SetP_o,
OB => Fmc0Ch1SetN_o
);
cFmc0Ch1ResObufds: OBUFDS
port map (
I => Fmc0Ch1Res,
O => Fmc0Ch1ResP_o,
OB => Fmc0Ch1ResN_o
);
cFmc0Ch2SetObufds: OBUFDS
port map (
I => Fmc0Ch2Set,
O => Fmc0Ch2SetP_o,
OB => Fmc0Ch2SetN_o
);
cFmc0Ch2ResObufds: OBUFDS
port map (
I => Fmc0Ch2Res,
O => Fmc0Ch2ResP_o,
OB => Fmc0Ch2ResN_o
);
cFmc0ClkOutOddr: ODDR2
generic map(
DDR_ALIGNMENT => "C0",
SRTYPE => "ASYNC"
)
port map (
Q => Fmc0ClkOutDdr,
C0 => Fmc0ClkOut_k,
C1 => not Fmc0ClkOut_k,
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0'
);
cFmc0ClkOutObufds: OBUFDS
port map (
I => Fmc0ClkOutDdr,
O => Fmc0ClkOutP_ok,
OB => Fmc0ClkOutN_ok
);
------------------------------------------------------------------------------
-- FMC Slot 1
------------------------------------------------------------------------------
cFmc1ClkIn0Ibufgds: IBUFGDS
generic map (
DIFF_TERM => TRUE
)
port map (
I => Fmc1ClkIn0P_ik,
IB => Fmc1ClkIn0N_ik,
O => Fmc1ClkIn0_k
);
cFmc1TriggerIbufds: IBUFDS
generic map (
DIFF_TERM => TRUE
)
port map (
I => Fmc1TriggerP_i,
IB => Fmc1TriggerN_i,
O => Fmc1Trigger
);
cFmc1FfpgCore: entity work.FfpgCore(syn)
generic map (
g_ClkFrequency => c_ClkSysFrequency -- input clock frequency in Hz
)
port map (
-- Wishbone connection
Clk_ik => ClkSys_k,
Reset_ira => Fmc1Reset_r, -- synchronized locally for better timing
Wb_i => CnxMasterOut(c_SlaveFmc1Id),
Wb_o => CnxMasterIn(c_SlaveFmc1Id),
---- FMC interface
-- clock
ClkIn0_ik => Fmc1ClkIn0_k,
-- DACs
TriggerDac_o => Fmc1TriggerDac_o,
VcxoDac_o => Fmc1VcxoDac_o,
-- output enable
Ch1OutputEnable_o => Fmc1Ch1OutputEnable_o,
Ch2OutputEnable_o => Fmc1Ch2OutputEnable_o,
-- delay configuration
DelayValue_ob => Fmc1DelayValue_ob,
Ch1SetLe_on => Fmc1Ch1SetLe_on,
Ch1ResLe_on => Fmc1Ch1ResLe_on,
Ch2SetLe_on => Fmc1Ch2SetLe_on,
Ch2ResLe_on => Fmc1Ch2ResLe_on,
Ch1Set_o => Fmc1Ch1Set,
Ch1Res_o => Fmc1Ch1Res,
Ch2Set_o => Fmc1Ch2Set,
Ch2Res_o => Fmc1Ch2Res,
Trigger_i => Fmc1Trigger,
-- AD9512 SPI
SpiAd9512Sclk_o => Fmc1SpiAd9512Sclk_o,
SpiAd9512Mosi_o => Fmc1SpiAd9512Mosi_o,
SpiAd9512Miso_i => Fmc1SpiAd9512Miso_i,
SpiAd9512Cs_on => Fmc1SpiAd9512Cs_on,
-- AD9512 func. pin
Ad9512Func_o => Fmc1Ad9512Func_o,
-- clock selection pin of SY58017U
Clk2Sel_o => Fmc1Clk2Sel_o,
-- clock output
ClkOut_ok => Fmc1ClkOut_k,
-- temperature chip interface
Onewire_io => Fmc1Onewire_io,
-- LEDs
Led_ob => Fmc1Led_ob
);
-- feedback loop to FP LEMO
FpLemo_ob4(1) <= Fmc1Ch1OutCal_i;
FpLemo_ob4(2) <= Fmc1Ch2OutCal_i;
FpLemoDir1_A2B_o <= '1';
FpLemoDir2_A2B_o <= '1';
FpLemoTerm_oeb4(2 downto 1) <= "00";
cFmc1Ch1SetObufds: OBUFDS
port map (
I => Fmc1Ch1Set,
O => Fmc1Ch1SetP_o,
OB => Fmc1Ch1SetN_o
);
cFmc1Ch1ResObufds: OBUFDS
port map (
I => Fmc1Ch1Res,
O => Fmc1Ch1ResP_o,
OB => Fmc1Ch1ResN_o
);
cFmc1Ch2SetObufds: OBUFDS
port map (
I => Fmc1Ch2Set,
O => Fmc1Ch2SetP_o,
OB => Fmc1Ch2SetN_o
);
cFmc1Ch2ResObufds: OBUFDS
port map (
I => Fmc1Ch2Res,
O => Fmc1Ch2ResP_o,
OB => Fmc1Ch2ResN_o
);
cFmc1ClkOutOddr: ODDR2
generic map(
DDR_ALIGNMENT => "C0",
SRTYPE => "ASYNC"
)
port map (
Q => Fmc1ClkOutDdr,
C0 => Fmc1ClkOut_k,
C1 => not Fmc1ClkOut_k,
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0'
);
cFmc1ClkOutObufds: OBUFDS
port map (
I => Fmc1ClkOutDdr,
O => Fmc1ClkOutP_ok,
OB => Fmc1ClkOutN_ok
);
end architecture;
-- -- Unused architecure need to be commented out - ISE doesn't know how to handle multiple architecure
-- -- for top level entity!
-- architecture FmcIoTest of SvecTopFfpg is
-- signal Fmc0ClkIn0_k, Fmc0Trigger: std_logic;
-- signal HeartBeat, InputOr: std_logic;
-- begin
-- -- DAC interface (20MHz and 25MHz VCXO)
-- Pll20DacDin_o <= '0';
-- Pll20DacSclk_o <= '0';
-- Pll20DacSync_on <= '1';
-- Pll25DacDin_o <= '0';
-- Pll25DacSclk_o <= '0';
-- Pll25DacSync_on <= '1';
-- -- Carrier font panel LEDs
-- FpLedsLineEnable_ob2 <= (others => '0');
-- FpLedsLine_ob2 <= (others => '0');
-- FpLedsColumn_ob4 <= (others => '0');
-- -- Carrier I2C eeprom
-- CarrierScl_io <= 'Z';
-- CarrierSda_io <= 'Z';
-- -- Carrier 1-wire interface (DS18B20 thermometer + unique ID)
-- CarrierOneWire_io <= 'Z';
-- ------------------------------------------
-- -- VME interface
-- ------------------------------------------
-- VmeRetry_oe_o <= '0';
-- VmeRetry_n_o <= '1';
-- VmeLword_n_b <= 'Z';
-- VmeIackout_n_o <= '1';
-- VmeDtack_oe_o <= '0';
-- VmeDtack_n_o <= '1';
-- VmeData_oe_n_o <= '1';
-- VmeData_dir_o <= '0';
-- VmeBerr_o <= '0';
-- VmeAddr_oe_n_o <= '1';
-- VmeAddr_dir_o <= '0';
-- VmeIrq_n_o <= (others => '1');
-- VmeData_b <= (others => 'Z');
-- VmeAddr_b <= (others => 'Z');
-- ------------------------------------------
-- -- Test stuff
-- ------------------------------------------
-- cHeartBeat: entity work.HeartBeat(syn)
-- generic map (
-- g_ClkFrequency => 20e6
-- )
-- port map (
-- Clk_ik => Clk20_ik,
-- Reset_ir => not Reset_inr,
-- HeartBeat_o => HeartBeat
-- );
-- ------------------------------------------
-- -- FMC slot 0
-- ------------------------------------------
-- -- DACs
-- Fmc0TriggerDac_o.FrameSynchronization_n <= HeartBeat;
-- Fmc0TriggerDac_o.SerialClock <= HeartBeat;
-- Fmc0TriggerDac_o.SerialData <= HeartBeat;
-- Fmc0VcxoDac_o.FrameSynchronization_n <= HeartBeat;
-- Fmc0VcxoDac_o.SerialClock <= HeartBeat;
-- Fmc0VcxoDac_o.SerialData <= HeartBeat;
-- -- output enable
-- Fmc0Ch1OutputEnable_o <= HeartBeat;
-- Fmc0Ch2OutputEnable_o <= HeartBeat;
-- -- delay configuration
-- Fmc0DelayValue_ob <= (others => HeartBeat);
-- Fmc0Ch1SetLe_o <= Fmc0ClkIn0_k;
-- Fmc0Ch1ResLe_o <= Fmc0Trigger;
-- Fmc0Ch2SetLe_o <= Fmc0SpiAd9512Miso_i;
-- Fmc0Ch2ResLe_o <= HeartBeat;
-- -- AD9512 SPI
-- Fmc0SpiAd9512Sclk_o <= HeartBeat;
-- Fmc0SpiAd9512Mosi_o <= HeartBeat;
-- Fmc0SpiAd9512Cs_on <= HeartBeat;
-- -- clock selection pin of SY58017U
-- Fmc0Clk2Sel_o <= HeartBeat;
-- -- temperature chip interface
-- Fmc0Onewire_io <= HeartBeat;
-- -- LEDs
-- Fmc0Led_ob <= (others => HeartBeat);
-- -- DS inputs
-- cFmc0ClkIn0Ibufgds: IBUFGDS
-- generic map (
-- DIFF_TERM => TRUE
-- )
-- port map (
-- I => Fmc0ClkIn0P_ik,
-- IB => Fmc0ClkIn0N_ik,
-- O => Fmc0ClkIn0_k
-- );
-- cFmc0TriggerIbufds: IBUFDS
-- generic map (
-- DIFF_TERM => TRUE
-- )
-- port map (
-- I => Fmc0TriggerP_i,
-- IB => Fmc0TriggerN_i,
-- O => Fmc0Trigger
-- );
-- -- DS outputs
-- cFmc0Ch1SetObufds: OBUFDS
-- port map (
-- I => HeartBeat,
-- O => Fmc0Ch1SetP_o,
-- OB => Fmc0Ch1SetN_o
-- );
-- cFmc0Ch1ResObufds: OBUFDS
-- port map (
-- I => HeartBeat,
-- O => Fmc0Ch1ResP_o,
-- OB => Fmc0Ch1ResN_o
-- );
-- cFmc0Ch2SetObufds: OBUFDS
-- port map (
-- I => HeartBeat,
-- O => Fmc0Ch2SetP_o,
-- OB => Fmc0Ch2SetN_o
-- );
-- cFmc0Ch2ResObufds: OBUFDS
-- port map (
-- I => HeartBeat,
-- O => Fmc0Ch2ResP_o,
-- OB => Fmc0Ch2ResN_o
-- );
-- end architecture;
hdl/svec/rtl/carrier_csr.vhd deleted 100644 → 0
View file @ 0ca74d29
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for SVEC carrier control and status registers
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : 12/19/16 17:04:37
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity carrier_csr is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'PCB revision' in reg: 'Carrier type and PCB version'
carrier_csr_carrier_pcb_rev_i : in std_logic_vector(4 downto 0);
-- Port for std_logic_vector field: 'Reserved register' in reg: 'Carrier type and PCB version'
carrier_csr_carrier_reserved_i : in std_logic_vector(10 downto 0);
-- Port for std_logic_vector field: 'Carrier type' in reg: 'Carrier type and PCB version'
carrier_csr_carrier_type_i : in std_logic_vector(15 downto 0);
-- Port for BIT field: 'FMC 1 presence' in reg: 'Status'
carrier_csr_stat_fmc0_pres_i : in std_logic;
-- Port for BIT field: 'FMC 2 presence' in reg: 'Status'
carrier_csr_stat_fmc1_pres_i : in std_logic;
-- Port for BIT field: 'System clock PLL status' in reg: 'Status'
carrier_csr_stat_sys_pll_lck_i : in std_logic;
-- Port for BIT field: 'NOT_IMPLEMENTED: DDR3 bank 4 calibration status' in reg: 'Status'
carrier_csr_stat_ddr0_cal_done_i : in std_logic;
-- Port for BIT field: 'NOT_IMPLEMENTED: DDR3 bank 5 calibration status' in reg: 'Status'
carrier_csr_stat_ddr1_cal_done_i : in std_logic;
-- Port for std_logic_vector field: 'NOT_IMPLEMENTED: Front panel LED manual control' in reg: 'Control'
carrier_csr_ctrl_fp_leds_man_o : out std_logic_vector(15 downto 0);
-- Ports for BIT field: 'State of the FMC 1 reset line' in reg: 'Reset Register'
carrier_csr_rst_fmc0_n_o : out std_logic;
carrier_csr_rst_fmc0_n_i : in std_logic;
carrier_csr_rst_fmc0_n_load_o : out std_logic;
-- Ports for BIT field: 'State of the FMC 2 reset line' in reg: 'Reset Register'
carrier_csr_rst_fmc1_n_o : out std_logic;
carrier_csr_rst_fmc1_n_i : in std_logic;
carrier_csr_rst_fmc1_n_load_o : out std_logic
);
end carrier_csr;
architecture syn of carrier_csr is
signal carrier_csr_ctrl_fp_leds_man_int : std_logic_vector(15 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic;
signal wr_int : std_logic;
signal rd_int : std_logic;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
carrier_csr_ctrl_fp_leds_man_int <= "0000000000000000";
carrier_csr_rst_fmc0_n_load_o <= '0';
carrier_csr_rst_fmc1_n_load_o <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
carrier_csr_rst_fmc0_n_load_o <= '0';
carrier_csr_rst_fmc1_n_load_o <= '0';
ack_in_progress <= '0';
else
carrier_csr_rst_fmc0_n_load_o <= '0';
carrier_csr_rst_fmc1_n_load_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
end if;
rddata_reg(4 downto 0) <= carrier_csr_carrier_pcb_rev_i;
rddata_reg(15 downto 5) <= carrier_csr_carrier_reserved_i;
rddata_reg(31 downto 16) <= carrier_csr_carrier_type_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= carrier_csr_stat_fmc0_pres_i;
rddata_reg(1) <= carrier_csr_stat_fmc1_pres_i;
rddata_reg(2) <= carrier_csr_stat_sys_pll_lck_i;
rddata_reg(3) <= carrier_csr_stat_ddr0_cal_done_i;
rddata_reg(4) <= carrier_csr_stat_ddr1_cal_done_i;
rddata_reg(31 downto 5) <= (others => 'X');
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
carrier_csr_ctrl_fp_leds_man_int <= wrdata_reg(15 downto 0);
end if;
rddata_reg(15 downto 0) <= carrier_csr_ctrl_fp_leds_man_int;
rddata_reg(31 downto 16) <= (others => 'X');
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
carrier_csr_rst_fmc0_n_load_o <= '1';
carrier_csr_rst_fmc1_n_load_o <= '1';
end if;
rddata_reg(0) <= carrier_csr_rst_fmc0_n_i;
rddata_reg(1) <= carrier_csr_rst_fmc1_n_i;
rddata_reg(31 downto 2) <= (others => 'X');
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- NOT_IMPLEMENTED: Front panel LED manual control
carrier_csr_ctrl_fp_leds_man_o <= carrier_csr_ctrl_fp_leds_man_int;
-- State of the FMC 1 reset line
carrier_csr_rst_fmc0_n_o <= wrdata_reg(0);
-- State of the FMC 2 reset line
carrier_csr_rst_fmc1_n_o <= wrdata_reg(1);
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (ack_in_progress or (wb_stb_i and wb_cyc_i));
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/svec/sim/testbench/ConfigSvec.svh deleted 100644 → 0
View file @ 0ca74d29
`ifndef CONFIG_SVEC_SVH
`define CONFIG_SVEC_SVH
`define WB_SVEC_VME_ADDRESS 0
`define WB_FFPG_BASE (`WB_SVEC_VME_ADDRESS + 'h2_0000)
`define WB_FFPG_SPI_BASE (`WB_FFPG_BASE + 'h1000)
`define WB_FFPG_OW_BASE (`WB_FFPG_BASE + 'h1100)
`define WB_FFPG_CSR_BASE (`WB_FFPG_BASE + 'h1_0000)
`define WB_FFPG_SPI_REG(REG_ADDRESS) (`WB_FFPG_SPI_BASE + REG_ADDRESS)
`define WB_FFPG_OW_REG(REG_ADDRESS) (`WB_FFPG_OW_BASE + REG_ADDRESS)
`define WB_FFPG_CSR_REG(REG_ADDRESS) (`WB_FFPG_CSR_BASE + REG_ADDRESS)
// SPI regs.
`define SPI_TX_RX_0 'h00
`define SPI_TX_RX_1 'h04
`define SPI_TX_RX_2 'h08
`define SPI_TX_RX_3 'h0c
`define SPI_CTRL 'h10
`define SPI_DIVIDER 'h14
`define SPI_SS 'h18
`endif //CONFIG_SVEC_SVH
hdl/svec/sim/testbench/SvecTopFfpgWrapper.vhd deleted 100644 → 0
View file @ 0ca74d29
-------------------------------------------------------------------------------
-- Title : Wrapper of SvecTopFfpg for SystemVerilog testbench
-- Project : FMC DEL 1ns 2cha (FFPG)
-- URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
-------------------------------------------------------------------------------
-- File : SvecTopFfpgWrapper.vhd
-- Author(s) : Jan Pospisil <j.pospisil@cern.ch>
-- Company : CERN (BE-BI-QP)
-- Created : 2016-08-03
-- Last update: 2016-08-24
-- Standard : VHDL2008
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CERN (BE-BI-QP)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author
-- 2016-08-24 1.0 Jan Pospisil
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.FfpgPkg.all;
entity SvecTopFfpgWrapper is
port (
-- Local 20MHz VCXO oscillator
Clk20_ik: in std_logic;
-- Reset from system fpga
Reset_inr: in std_logic;
-- DAC interface (20MHz and 25MHz VCXO)
Pll20DacDin_o: out std_logic;
Pll20DacSclk_o: out std_logic;
Pll20DacSync_on: out std_logic;
Pll25DacDin_o: out std_logic;
Pll25DacSclk_o: out std_logic;
Pll25DacSync_on: out std_logic;
-- Carrier font panel LEDs
FpLedsLineEnable_ob2: out std_logic_vector(1 downto 0);
FpLedsLine_ob2: out std_logic_vector(1 downto 0);
FpLedsColumn_ob4: out std_logic_vector(3 downto 0);
-- Carrier I2C eeprom
CarrierScl_io: inout std_logic;
CarrierSda_io: inout std_logic;
-- PCB revision
PcbRev_i: in std_logic_vector(4 downto 0);
-- Carrier 1-wire interface (DS18B20 thermometer + unique ID)
CarrierOneWire_io: inout std_logic;
------------------------------------------
-- VME interface
------------------------------------------
VmeWrite_n_i : in std_logic;
VmeSysreset_n_i : in std_logic;
VmeRetry_oe_o : out std_logic;
VmeRetry_n_o : out std_logic;
VmeLword_n_b : inout std_logic;
VmeIackout_n_o : out std_logic;
VmeIackin_n_i : in std_logic;
VmeIack_n_i : in std_logic;
VmeDtack_oe_o : out std_logic;
VmeDtack_n_o : out std_logic;
VmeDs_n_i : in std_logic_vector(1 downto 0);
VmeData_oe_n_o : out std_logic;
VmeData_dir_o : out std_logic;
VmeBerr_o : out std_logic;
VmeAs_n_i : in std_logic;
VmeAddr_oe_n_o : out std_logic;
VmeAddr_dir_o : out std_logic;
VmeIrq_n_o : out std_logic_vector(7 downto 1);
VmeGa_i : in std_logic_vector(5 downto 0);
VmeData_b : inout std_logic_vector(31 downto 0);
VmeAm_i : in std_logic_vector(5 downto 0);
VmeAddr_b : inout std_logic_vector(31 downto 1);
------------------------------------------
-- FMC slot management
------------------------------------------
Fmc0Present_in: in std_logic; -- Mezzanine present (active low)
-- Fmc0Scl: inout std_logic; -- Mezzanine system I2C clock (EEPROM)
-- Fmc0Sda: inout std_logic; -- Mezzanine system I2C data (EEPROM)
Fmc1Present_in: in std_logic; -- Mezzanine present (active low)
-- Fmc1Scl: inout std_logic; -- Mezzanine system I2C clock (EEPROM)
-- Fmc1Sda: inout std_logic; -- Mezzanine system I2C data (EEPROM)
------------------------------------------
-- FMC slot 0
------------------------------------------
-- clock
Fmc0ClkIn0P_ik: in std_logic;
Fmc0ClkIn0N_ik: in std_logic;
-- DACs
Fmc0TriggerDac_o_FrameSynchronization_n: out std_logic;
Fmc0TriggerDac_o_SerialClock: out std_logic;
Fmc0TriggerDac_o_SerialData: out std_logic;
Fmc0VcxoDac_o_FrameSynchronization_n: out std_logic;
Fmc0VcxoDac_o_SerialClock: out std_logic;
Fmc0VcxoDac_o_SerialData: out std_logic;
-- output enable
Fmc0Ch1OutputEnable_o: out std_logic;
Fmc0Ch2OutputEnable_o: out std_logic;
-- signal feedback
Fmc0Ch1OutCal_i: in std_logic;
Fmc0Ch2OutCal_i: in std_logic;
-- delay configuration
Fmc0DelayValue_ob: out std_logic_vector(9 downto 0);
Fmc0Ch1SetLe_on: out std_logic;
Fmc0Ch1ResLe_on: out std_logic;
Fmc0Ch2SetLe_on: out std_logic;
Fmc0Ch2ResLe_on: out std_logic;
Fmc0Ch1SetP_o: out std_logic;
Fmc0Ch1SetN_o: out std_logic;
Fmc0Ch1ResP_o: out std_logic;
Fmc0Ch1ResN_o: out std_logic;
Fmc0Ch2SetP_o: out std_logic;
Fmc0Ch2SetN_o: out std_logic;
Fmc0Ch2ResP_o: out std_logic;
Fmc0Ch2ResN_o: out std_logic;
Fmc0TriggerP_i: in std_logic;
Fmc0TriggerN_i: in std_logic;
-- AD9512 SPI
Fmc0SpiAd9512Sclk_o: out std_logic;
Fmc0SpiAd9512Mosi_o: out std_logic;
Fmc0SpiAd9512Miso_i: in std_logic;
Fmc0SpiAd9512Cs_on: out std_logic;
-- AD9512 func. pin
Fmc0Ad9512Func_o: out std_logic;
-- clock selection pin of SY58017U
Fmc0Clk2Sel_o: out std_logic;
-- clock output
Fmc0ClkOutP_ok: out std_logic;
Fmc0ClkOutN_ok: out std_logic;
-- temperature chip interface
Fmc0Onewire_io: inout std_logic;
-- LEDs
Fmc0Led_ob: out std_logic_vector(4 downto 1);
------------------------------------------
-- FMC slot 1
------------------------------------------
-- clock
Fmc1ClkIn0P_ik: in std_logic;
Fmc1ClkIn0N_ik: in std_logic;
-- DACs
Fmc1TriggerDac_o_FrameSynchronization_n: out std_logic;
Fmc1TriggerDac_o_SerialClock: out std_logic;
Fmc1TriggerDac_o_SerialData: out std_logic;
Fmc1VcxoDac_o_FrameSynchronization_n: out std_logic;
Fmc1VcxoDac_o_SerialClock: out std_logic;
Fmc1VcxoDac_o_SerialData: out std_logic;
-- output enable
Fmc1Ch1OutputEnable_o: out std_logic;
Fmc1Ch2OutputEnable_o: out std_logic;
-- signal feedback
Fmc1Ch1OutCal_i: in std_logic;
Fmc1Ch2OutCal_i: in std_logic;
-- delay configuration
Fmc1DelayValue_ob: out std_logic_vector(9 downto 0);
Fmc1Ch1SetLe_on: out std_logic;
Fmc1Ch1ResLe_on: out std_logic;
Fmc1Ch2SetLe_on: out std_logic;
Fmc1Ch2ResLe_on: out std_logic;
Fmc1Ch1SetP_o: out std_logic;
Fmc1Ch1SetN_o: out std_logic;
Fmc1Ch1ResP_o: out std_logic;
Fmc1Ch1ResN_o: out std_logic;
Fmc1Ch2SetP_o: out std_logic;
Fmc1Ch2SetN_o: out std_logic;
Fmc1Ch2ResP_o: out std_logic;
Fmc1Ch2ResN_o: out std_logic;
Fmc1TriggerP_i: in std_logic;
Fmc1TriggerN_i: in std_logic;
-- AD9512 SPI
Fmc1SpiAd9512Sclk_o: out std_logic;
Fmc1SpiAd9512Mosi_o: out std_logic;
Fmc1SpiAd9512Miso_i: in std_logic;
Fmc1SpiAd9512Cs_on: out std_logic;
-- AD9512 func. pin
Fmc1Ad9512Func_o: out std_logic;
-- clock selection pin of SY58017U
Fmc1Clk2Sel_o: out std_logic;
-- clock output
Fmc1ClkOutP_ok: out std_logic;
Fmc1ClkOutN_ok: out std_logic;
-- temperature chip interface
Fmc1Onewire_io: inout std_logic;
-- LEDs
Fmc1Led_ob: out std_logic_vector(4 downto 1)
);
end entity;
architecture wrapper of SvecTopFfpgWrapper is
signal Fmc0TriggerDac_o, Fmc0VcxoDac_o: t_Ad5600Interface;
signal Fmc0DelayValue_ob_unsigned: unsigned(9 downto 0);
signal Fmc1TriggerDac_o, Fmc1VcxoDac_o: t_Ad5600Interface;
signal Fmc1DelayValue_ob_unsigned: unsigned(9 downto 0);
begin
cSvecTopFfpg: entity work.SvecTopFfpg(rtl)
port map (
Clk20_ik => Clk20_ik,
Reset_inr => Reset_inr,
Pll20DacDin_o => Pll20DacDin_o,
Pll20DacSclk_o => Pll20DacSclk_o,
Pll20DacSync_on => Pll20DacSync_on,
Pll25DacDin_o => Pll25DacDin_o,
Pll25DacSclk_o => Pll25DacSclk_o,
Pll25DacSync_on => Pll25DacSync_on,
FpLedsLineEnable_ob2 => FpLedsLineEnable_ob2,
FpLedsLine_ob2 => FpLedsLine_ob2,
FpLedsColumn_ob4 => FpLedsColumn_ob4,
CarrierScl_io => CarrierScl_io,
CarrierSda_io => CarrierSda_io,
PcbRev_i => PcbRev_i,
CarrierOneWire_io => CarrierOneWire_io,
------------------------------------------
-- VME interface
------------------------------------------
VmeWrite_n_i => VmeWrite_n_i,
VmeSysreset_n_i => VmeSysreset_n_i,
VmeRetry_oe_o => VmeRetry_oe_o,
VmeRetry_n_o => VmeRetry_n_o,
VmeLword_n_b => VmeLword_n_b,
VmeIackout_n_o => VmeIackout_n_o,
VmeIackin_n_i => VmeIackin_n_i,
VmeIack_n_i => VmeIack_n_i,
VmeDtack_oe_o => VmeDtack_oe_o,
VmeDtack_n_o => VmeDtack_n_o,
VmeDs_n_i => VmeDs_n_i,
VmeData_oe_n_o => VmeData_oe_n_o,
VmeData_dir_o => VmeData_dir_o,
VmeBerr_o => VmeBerr_o,
VmeAs_n_i => VmeAs_n_i,
VmeAddr_oe_n_o => VmeAddr_oe_n_o,
VmeAddr_dir_o => VmeAddr_dir_o,
VmeIrq_n_o => VmeIrq_n_o,
VmeGa_i => VmeGa_i,
VmeData_b => VmeData_b,
VmeAm_i => VmeAm_i,
VmeAddr_b => VmeAddr_b,
------------------------------------------
-- FMC slot management
------------------------------------------
Fmc0Present_in => Fmc0Present_in, -- Mezzanine present (active low)
Fmc1Present_in => Fmc1Present_in, -- Mezzanine present (active low)
------------------------------------------
-- FMC slot 0
------------------------------------------
Fmc0ClkIn0P_ik => Fmc0ClkIn0P_ik,
Fmc0ClkIn0N_ik => Fmc0ClkIn0N_ik,
Fmc0TriggerDac_o.FrameSynchronization_n => Fmc0TriggerDac_o_FrameSynchronization_n,
Fmc0TriggerDac_o.SerialClock => Fmc0TriggerDac_o_SerialClock,
Fmc0TriggerDac_o.SerialData => Fmc0TriggerDac_o_SerialData,
Fmc0VcxoDac_o.FrameSynchronization_n => Fmc0VcxoDac_o_FrameSynchronization_n,
Fmc0VcxoDac_o.SerialClock => Fmc0VcxoDac_o_SerialClock,
Fmc0VcxoDac_o.SerialData => Fmc0VcxoDac_o_SerialData,
Fmc0Ch1OutputEnable_o => Fmc0Ch1OutputEnable_o,
Fmc0Ch2OutputEnable_o => Fmc0Ch2OutputEnable_o,
Fmc0Ch1OutCal_i => Fmc0Ch1OutCal_i,
Fmc0Ch2OutCal_i => Fmc0Ch2OutCal_i,
Fmc0DelayValue_ob => Fmc0DelayValue_ob_unsigned,
Fmc0Ch1SetLe_on => Fmc0Ch1SetLe_on,
Fmc0Ch1ResLe_on => Fmc0Ch1ResLe_on,
Fmc0Ch2SetLe_on => Fmc0Ch2SetLe_on,
Fmc0Ch2ResLe_on => Fmc0Ch2ResLe_on,
Fmc0Ch1SetP_o => Fmc0Ch1SetP_o,
Fmc0Ch1SetN_o => Fmc0Ch1SetN_o,
Fmc0Ch1ResP_o => Fmc0Ch1ResP_o,
Fmc0Ch1ResN_o => Fmc0Ch1ResN_o,
Fmc0Ch2SetP_o => Fmc0Ch2SetP_o,
Fmc0Ch2SetN_o => Fmc0Ch2SetN_o,
Fmc0Ch2ResP_o => Fmc0Ch2ResP_o,
Fmc0Ch2ResN_o => Fmc0Ch2ResN_o,
Fmc0TriggerP_i => Fmc0TriggerP_i,
Fmc0TriggerN_i => Fmc0TriggerN_i,
Fmc0SpiAd9512Sclk_o => Fmc0SpiAd9512Sclk_o,
Fmc0SpiAd9512Mosi_o => Fmc0SpiAd9512Mosi_o,
Fmc0SpiAd9512Miso_i => Fmc0SpiAd9512Miso_i,
Fmc0SpiAd9512Cs_on => Fmc0SpiAd9512Cs_on,
Fmc0Ad9512Func_o => Fmc0Ad9512Func_o,
Fmc0Clk2Sel_o => Fmc0Clk2Sel_o,
Fmc0ClkOutP_ok => Fmc0ClkOutP_ok,
Fmc0ClkOutN_ok => Fmc0ClkOutN_ok,
Fmc0Onewire_io => Fmc0Onewire_io,
Fmc0Led_ob => Fmc0Led_ob,
------------------------------------------
-- FMC slot 1
------------------------------------------
Fmc1ClkIn0P_ik => Fmc1ClkIn0P_ik,
Fmc1ClkIn0N_ik => Fmc1ClkIn0N_ik,
Fmc1TriggerDac_o.FrameSynchronization_n => Fmc1TriggerDac_o_FrameSynchronization_n,
Fmc1TriggerDac_o.SerialClock => Fmc1TriggerDac_o_SerialClock,
Fmc1TriggerDac_o.SerialData => Fmc1TriggerDac_o_SerialData,
Fmc1VcxoDac_o.FrameSynchronization_n => Fmc1VcxoDac_o_FrameSynchronization_n,
Fmc1VcxoDac_o.SerialClock => Fmc1VcxoDac_o_SerialClock,
Fmc1VcxoDac_o.SerialData => Fmc1VcxoDac_o_SerialData,
Fmc1Ch1OutputEnable_o => Fmc1Ch1OutputEnable_o,
Fmc1Ch2OutputEnable_o => Fmc1Ch2OutputEnable_o,
Fmc1Ch1OutCal_i => Fmc1Ch1OutCal_i,
Fmc1Ch2OutCal_i => Fmc1Ch2OutCal_i,
Fmc1DelayValue_ob => Fmc1DelayValue_ob_unsigned,
Fmc1Ch1SetLe_on => Fmc1Ch1SetLe_on,
Fmc1Ch1ResLe_on => Fmc1Ch1ResLe_on,
Fmc1Ch2SetLe_on => Fmc1Ch2SetLe_on,
Fmc1Ch2ResLe_on => Fmc1Ch2ResLe_on,
Fmc1Ch1SetP_o => Fmc1Ch1SetP_o,
Fmc1Ch1SetN_o => Fmc1Ch1SetN_o,
Fmc1Ch1ResP_o => Fmc1Ch1ResP_o,
Fmc1Ch1ResN_o => Fmc1Ch1ResN_o,
Fmc1Ch2SetP_o => Fmc1Ch2SetP_o,
Fmc1Ch2SetN_o => Fmc1Ch2SetN_o,
Fmc1Ch2ResP_o => Fmc1Ch2ResP_o,
Fmc1Ch2ResN_o => Fmc1Ch2ResN_o,
Fmc1TriggerP_i => Fmc1TriggerP_i,
Fmc1TriggerN_i => Fmc1TriggerN_i,
Fmc1SpiAd9512Sclk_o => Fmc1SpiAd9512Sclk_o,
Fmc1SpiAd9512Mosi_o => Fmc1SpiAd9512Mosi_o,
Fmc1SpiAd9512Miso_i => Fmc1SpiAd9512Miso_i,
Fmc1SpiAd9512Cs_on => Fmc1SpiAd9512Cs_on,
Fmc1Ad9512Func_o => Fmc1Ad9512Func_o,
Fmc1Clk2Sel_o => Fmc1Clk2Sel_o,
Fmc1ClkOutP_ok => Fmc1ClkOutP_ok,
Fmc1ClkOutN_ok => Fmc1ClkOutN_ok,
Fmc1Onewire_io => Fmc1Onewire_io,
Fmc1Led_ob => Fmc1Led_ob
);
Fmc0DelayValue_ob <= std_logic_vector(Fmc0DelayValue_ob_unsigned);
Fmc1DelayValue_ob <= std_logic_vector(Fmc1DelayValue_ob_unsigned);
end architecture;
hdl/svec/sim/testbench/Testbench.sv deleted 100644 → 0
View file @ 0ca74d29
//-----------------------------------------------------------------------------
// Title : Testbench for implementation on SVEC carrier card
// Project : FMC DEL 1ns 2cha (FFPG)
// URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
//-----------------------------------------------------------------------------
// File : Testbench.sv
// Author(s) : Jan Pospisil <j.pospisil@cern.ch>
// Company : CERN (BE-BI-QP)
// Created : 2016-08-03
// Last update: 2016-08-24
// Standard : SystemVerilog
//-----------------------------------------------------------------------------
// Description:
//-----------------------------------------------------------------------------
// Copyright (c) 2016 CERN (BE-BI-QP)
//-----------------------------------------------------------------------------
// GNU LESSER GENERAL PUBLIC LICENSE
//-----------------------------------------------------------------------------
// This source file is free software; you can redistribute it and/or modify it
// under the terms of the GNU Lesser General Public License as published by the
// Free Software Foundation; either version 2.1 of the License, or (at your
// option) any later version. This source is distributed in the hope that it
// will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
// of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU Lesser General Public License for more details. You should have
// received a copy of the GNU Lesser General Public License along with this
// source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
//-----------------------------------------------------------------------------
// Revisions :
// Date Version Author
// 2016-08-24 1.0 Jan Pospisil
//-----------------------------------------------------------------------------
`include "vme64x_bfm.svh"
`include "svec_vme_buffers.svh"
`include "fmc.svh"
`include "../../../ffpg/sim/testbench/ffpg_csr.svh"
`include "carrier_csr.svh"
`include "ConfigSvec.svh"
module Testbench;
reg Reset_inr = 0;
reg Clk20_ik = 0;
reg ClkRf_k = 0;
reg Trigger = 0;
int BunchCounter = 0;
always #25ns Clk20_ik <= ~Clk20_ik;
always #5ns ClkRf_k <= ~ClkRf_k; // 200 MHz
always_ff @(posedge ClkRf_k) begin
if (BunchCounter == 17820) begin
BunchCounter <= 0;
Trigger <= 1;
end else begin
BunchCounter <= BunchCounter + 1;
Trigger <= 0;
end
end
initial begin
#10us; // for PLL lock and reset settle
repeat(20) @(posedge Clk20_ik);
Reset_inr = 1;
end
IVME64X VME(Reset_inr);
`DECLARE_VME_BUFFERS(VME.slave);
`DECLARE_FMC(0);
`DECLARE_FMC(1);
logic [1:0] FpLedsLineEnable_ob2;
logic [1:0] FpLedsLine_ob2;
logic [3:0] FpLedsColumn_ob4;
wire CarrierScl_io;
wire CarrierSda_io;
wire CarrierOneWire_io;
pullup(CarrierScl_io);
pullup(CarrierSda_io);
CBusAccessor_VME64x acc;
SvecTopFfpgWrapper cDut (
.Clk20_ik(Clk20_ik),
.Reset_inr(Reset_inr),
.Pll20DacDin_o(),
.Pll20DacSclk_o(),
.Pll20DacSync_on(),
.Pll25DacDin_o(),
.Pll25DacSclk_o(),
.Pll25DacSync_on(),
.FpLedsLineEnable_ob2(FpLedsLineEnable_ob2),
.FpLedsLine_ob2(FpLedsLine_ob2),
.FpLedsColumn_ob4(FpLedsColumn_ob4),
.CarrierScl_io(CarrierScl_io),
.CarrierSda_io(CarrierSda_io),
.PcbRev_i(5'b00001),
.CarrierOneWire_io(CarrierOneWire_io),
`WIRE_FMC(0)
`WIRE_FMC(1)
`WIRE_VME_PINS(8) // slot number in parameter // don't change that magic 8 - it's hardcoded somewhere else
);
assign Fmc0Present_in = 1;
assign Fmc0ClkIn0P_ik = ClkRf_k;
assign Fmc0ClkIn0N_ik = ~Fmc0ClkIn0P_ik;
assign Fmc0TriggerP_i = Trigger;
assign Fmc0TriggerN_i = ~Fmc0TriggerP_i;
assign Fmc0SpiAd9512Miso_i = Fmc0SpiAd9512Mosi_o; // loopback
assign Fmc1Present_in = 1;
assign Fmc1ClkIn0P_ik = ClkRf_k;
assign Fmc1ClkIn0N_ik = ~Fmc1ClkIn0P_ik;
assign Fmc1TriggerP_i = Trigger;
assign Fmc1TriggerN_i = ~Fmc1TriggerP_i;
assign Fmc1SpiAd9512Miso_i = Fmc1SpiAd9512Mosi_o; // loopback
task automatic init_vme64x_core;
/* map func0 to 0x80000000, A32 */
acc.write('h7ff63, 'h80, A32|CR_CSR|D08Byte3); // maybe here?
acc.write('h7ff67, 0, CR_CSR|A32|D08Byte3);
acc.write('h7ff6b, 0, CR_CSR|A32|D08Byte3);
acc.write('h7ff6f, 36, CR_CSR|A32|D08Byte3);
acc.write('h7ff33, 1, CR_CSR|A32|D08Byte3);
acc.write('h7fffb, 'h10, CR_CSR|A32|D08Byte3); /* enable module (BIT_SET = 0x10) */
acc.set_default_modifiers(A32 | D32 | SINGLE);
endtask
task automatic WbWrite(uint32_t address, uint32_t data, string label = "");
uint64_t data64 = data;
if (label != "")
$display(label);
acc.write(address, data64, A32|SINGLE|D32);
$display("[0x%x]: 0x%x", address, data);
#1us; // not to issue commands too fast, to better simulate real behaviour
endtask
task automatic WbRead(uint32_t address, output uint32_t data, input string label = "");
uint64_t data64;
if (label != "")
$display(label);
acc.read(address, data64, A32|SINGLE|D32);
$display("[0x%x]: 0x%x", address, data64[31:0]);
data = data64[31:0];
#1us; // not to issue commands too fast, to better simulate real behaviour
endtask
task automatic TestSdb;
uint64_t d;
uint32_t base;
uint32_t address;
int i;
base = `WB_SVEC_VME_ADDRESS;
$display("Carrier SDB:");
for (i=0; i<64; i = i+4) begin
address = base + i;
acc.read(address, d, A32|SINGLE|D32);
$display("[0x%x]: 0x%x", address, d[31:0]);
end
base = `WB_FFPG_BASE + 64*0;
$display("FFPG SDB:");
for (i=0; i<64; i = i+4) begin
address = base + i;
acc.read(address, d, A32|SINGLE|D32);
$display("[0x%x]: 0x%x", address, d[31:0]);
end
endtask
task automatic TestFfpgCsr;
uint64_t d;
uint32_t base;
uint32_t address;
address = `WB_FFPG_CSR_REG(`ADDR_FFPG_STATUS);
$display("FFPG Status reg.:");
acc.read(address, d, A32|SINGLE|D32);
$display("[0x%x]: 0x%x", address, d[31:0]);
address = `WB_FFPG_CSR_REG(`ADDR_FFPG_CONTROL);
$display("Control reg. write:");
d = 4;
acc.write(address, d, A32|SINGLE|D32);
$display("[0x%x]: 0x%x", address, d[31:0]);
address = `WB_FFPG_CSR_REG(`ADDR_FFPG_STATUS);
$display("FFPG Status reg.:");
acc.read(address, d, A32|SINGLE|D32);
$display("[0x%x]: 0x%x", address, d[31:0]);
endtask
task automatic TestReal;
`include "z:/FFPG/wb_trace.svh"
// #1ms;
// WbRead(`WB_FFPG_CSR_REG(`ADDR_FFPG_DEBUG), dataOut, "Debug");
endtask
task automatic TestAd9512Sync;
uint32_t data;
WbWrite(`WB_FFPG_CSR_REG(`ADDR_FFPG_CONTROL), 'h200);
WbRead(`WB_FFPG_CSR_REG(`ADDR_FFPG_CONTROL), data);
#200us;
WbRead(`WB_FFPG_CSR_REG(`ADDR_FFPG_CONTROL), data);
endtask
task automatic WaitUntilReady;
uint32_t data;
do
WbRead(`WB_FFPG_CSR_REG(`ADDR_FFPG_STATUS), data);
while (data & 'b1111);
endtask
initial begin
acc = new(VME);
#10us; // for PLL lock and reset settle
#20us;
init_vme64x_core;
WaitUntilReady;
#5us
// TestSdb;
// TestFfpgCsr;
TestReal;
// TestAd9512Sync;
// TestAd9512Sync;
// uint64_t blt_addr[];
// uint64_t blt_data[];
// $display("Write data to DDR in BLT\n");
// blt_addr = {'h3000};
// blt_data = {'h1, 'h2, 'h3, 'h4, 'h5, 'h6, 'h7, 'h8 ,'h9, 'hA};
// acc.writem(blt_addr, blt_data, A32|BLT|D32, result);
// $display("Read data from DDR in BLT");
// blt_data = {};
// acc.readm(blt_addr, blt_data, A32|BLT|D32, result);
// for(i=0; i<10; i++) begin
// $display("Data %d: 0x%x\n", i, blt_data[i]);
// end
$stop;
end
endmodule
hdl/svec/sim/testbench/carrier_csr.svh deleted 100644 → 0
View file @ 0ca74d29
`define ADDR_CARRIER_CSR_CARRIER 4'h0
`define CARRIER_CSR_CARRIER_PCB_REV_OFFSET 0
`define CARRIER_CSR_CARRIER_PCB_REV 32'h0000001f
`define CARRIER_CSR_CARRIER_RESERVED_OFFSET 5
`define CARRIER_CSR_CARRIER_RESERVED 32'h0000ffe0
`define CARRIER_CSR_CARRIER_TYPE_OFFSET 16
`define CARRIER_CSR_CARRIER_TYPE 32'hffff0000
`define ADDR_CARRIER_CSR_STAT 4'h4
`define CARRIER_CSR_STAT_FMC0_PRES_OFFSET 0
`define CARRIER_CSR_STAT_FMC0_PRES 32'h00000001
`define CARRIER_CSR_STAT_FMC1_PRES_OFFSET 1
`define CARRIER_CSR_STAT_FMC1_PRES 32'h00000002
`define CARRIER_CSR_STAT_SYS_PLL_LCK_OFFSET 2
`define CARRIER_CSR_STAT_SYS_PLL_LCK 32'h00000004
`define CARRIER_CSR_STAT_DDR0_CAL_DONE_OFFSET 3
`define CARRIER_CSR_STAT_DDR0_CAL_DONE 32'h00000008
`define CARRIER_CSR_STAT_DDR1_CAL_DONE_OFFSET 4
`define CARRIER_CSR_STAT_DDR1_CAL_DONE 32'h00000010
`define ADDR_CARRIER_CSR_CTRL 4'h8
`define CARRIER_CSR_CTRL_FP_LEDS_MAN_OFFSET 0
`define CARRIER_CSR_CTRL_FP_LEDS_MAN 32'h0000ffff
`define ADDR_CARRIER_CSR_RST 4'hc
`define CARRIER_CSR_RST_FMC0_N_OFFSET 0
`define CARRIER_CSR_RST_FMC0_N 32'h00000001
`define CARRIER_CSR_RST_FMC1_N_OFFSET 1
`define CARRIER_CSR_RST_FMC1_N 32'h00000002
hdl/svec/sim/testbench/components/sn74vmeh22501.v deleted 100644 → 0
View file @ 0ca74d29
// http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw/repository/revisions/master/changes/hdl/svec/sim/vme64x_bfm/components/sn74vmeh22501.v
`timescale 1ns/1ns
module sn74vmeh22501 (
input oeab1,
oeby1_n,
a1,
output y1,
inout b1,
input oeab2,
oeby2_n,
a2,
output y2,
inout b2,
input oe_n,
input dir,
clkab,
le,
clkba,
inout [1:8] a3,
inout [1:8] b3);
assign b1 = oeab1 ? a1 : 1'bz;
assign y1 = oeby1_n ? 1'bz : b1;
assign b2 = oeab2 ? a2 : 1'bz;
assign y2 = oeby2_n ? 1'bz : b2;
reg [1:8] b3LFF;
always @(posedge clkab) if (~le) b3LFF <= #1 a3;
always @* if (le) b3LFF = a3;
assign b3 = (~oe_n && dir) ? b3LFF : 8'hz;
reg [1:8] a3LFF;
always @(posedge clkba) if (~le) a3LFF <= #1 b3;
always @* if (le) a3LFF = b3;
assign a3 = (~oe_n && ~dir) ? a3LFF : 8'hz;
endmodule
hdl/svec/sim/testbench/fmc.svh deleted 100644 → 0
View file @ 0ca74d29
`define DECLARE_FMC(__nb) \
logic Fmc``__nb``ClkIn0P_ik; \
logic Fmc``__nb``ClkIn0N_ik; \
logic Fmc``__nb``TriggerDac_o_FrameSynchronization_n; \
logic Fmc``__nb``TriggerDac_o_SerialClock; \
logic Fmc``__nb``TriggerDac_o_SerialData; \
logic Fmc``__nb``VcxoDac_o_FrameSynchronization_n; \
logic Fmc``__nb``VcxoDac_o_SerialClock; \
logic Fmc``__nb``VcxoDac_o_SerialData; \
logic Fmc``__nb``Ch1OutputEnable_o; \
logic Fmc``__nb``Ch2OutputEnable_o; \
logic Fmc``__nb``Ch1OutCal_i; \
logic Fmc``__nb``Ch2OutCal_i; \
logic [9:0] Fmc``__nb``DelayValue_ob; \
logic Fmc``__nb``Ch1SetLe_on; \
logic Fmc``__nb``Ch1ResLe_on; \
logic Fmc``__nb``Ch2SetLe_on; \
logic Fmc``__nb``Ch2ResLe_on; \
logic Fmc``__nb``Ch1SetP_o; \
logic Fmc``__nb``Ch1SetN_o; \
logic Fmc``__nb``Ch1ResP_o; \
logic Fmc``__nb``Ch1ResN_o; \
logic Fmc``__nb``Ch2SetP_o; \
logic Fmc``__nb``Ch2SetN_o; \
logic Fmc``__nb``Ch2ResP_o; \
logic Fmc``__nb``Ch2ResN_o; \
logic Fmc``__nb``TriggerP_i; \
logic Fmc``__nb``TriggerN_i; \
logic Fmc``__nb``SpiAd9512Sclk_o; \
logic Fmc``__nb``SpiAd9512Mosi_o; \
logic Fmc``__nb``SpiAd9512Miso_i; \
logic Fmc``__nb``SpiAd9512Cs_on; \
logic Fmc``__nb``Ad9512Func_o; \
logic Fmc``__nb``Clk2Sel_o; \
logic Fmc``__nb``ClkOutP_ok; \
logic Fmc``__nb``ClkOutN_ok; \
wire Fmc``__nb``Onewire_io; \
logic [4:1] Fmc``__nb``Led_ob; \
logic Fmc``__nb``Present_in;
`define WIRE_FMC(__nb) \
.Fmc``__nb``ClkIn0P_ik(Fmc``__nb``ClkIn0P_ik), \
.Fmc``__nb``ClkIn0N_ik(Fmc``__nb``ClkIn0N_ik), \
.Fmc``__nb``TriggerDac_o_FrameSynchronization_n(Fmc``__nb``TriggerDac_o_FrameSynchronization_n), \
.Fmc``__nb``TriggerDac_o_SerialClock(Fmc``__nb``TriggerDac_o_SerialClock), \
.Fmc``__nb``TriggerDac_o_SerialData(Fmc``__nb``TriggerDac_o_SerialData), \
.Fmc``__nb``VcxoDac_o_FrameSynchronization_n(Fmc``__nb``VcxoDac_o_FrameSynchronization_n), \
.Fmc``__nb``VcxoDac_o_SerialClock(Fmc``__nb``VcxoDac_o_SerialClock), \
.Fmc``__nb``VcxoDac_o_SerialData(Fmc``__nb``VcxoDac_o_SerialData), \
.Fmc``__nb``Ch1OutputEnable_o(Fmc``__nb``Ch1OutputEnable_o), \
.Fmc``__nb``Ch2OutputEnable_o(Fmc``__nb``Ch2OutputEnable_o), \
.Fmc``__nb``Ch1OutCal_i(Fmc``__nb``Ch1OutCal_i), \
.Fmc``__nb``Ch2OutCal_i(Fmc``__nb``Ch2OutCal_i), \
.Fmc``__nb``DelayValue_ob(Fmc``__nb``DelayValue_ob), \
.Fmc``__nb``Ch1SetLe_on(Fmc``__nb``Ch1SetLe_on), \
.Fmc``__nb``Ch1ResLe_on(Fmc``__nb``Ch1ResLe_on), \
.Fmc``__nb``Ch2SetLe_on(Fmc``__nb``Ch2SetLe_on), \
.Fmc``__nb``Ch2ResLe_on(Fmc``__nb``Ch2ResLe_on), \
.Fmc``__nb``Ch1SetP_o(Fmc``__nb``Ch1SetP_o), \
.Fmc``__nb``Ch1SetN_o(Fmc``__nb``Ch1SetN_o), \
.Fmc``__nb``Ch1ResP_o(Fmc``__nb``Ch1ResP_o), \
.Fmc``__nb``Ch1ResN_o(Fmc``__nb``Ch1ResN_o), \
.Fmc``__nb``Ch2SetP_o(Fmc``__nb``Ch2SetP_o), \
.Fmc``__nb``Ch2SetN_o(Fmc``__nb``Ch2SetN_o), \
.Fmc``__nb``Ch2ResP_o(Fmc``__nb``Ch2ResP_o), \
.Fmc``__nb``Ch2ResN_o(Fmc``__nb``Ch2ResN_o), \
.Fmc``__nb``TriggerP_i(Fmc``__nb``TriggerP_i), \
.Fmc``__nb``TriggerN_i(Fmc``__nb``TriggerN_i), \
.Fmc``__nb``SpiAd9512Sclk_o(Fmc``__nb``SpiAd9512Sclk_o), \
.Fmc``__nb``SpiAd9512Mosi_o(Fmc``__nb``SpiAd9512Mosi_o), \
.Fmc``__nb``SpiAd9512Miso_i(Fmc``__nb``SpiAd9512Miso_i), \
.Fmc``__nb``SpiAd9512Cs_on(Fmc``__nb``SpiAd9512Cs_on), \
.Fmc``__nb``Ad9512Func_o(Fmc``__nb``Ad9512Func_o), \
.Fmc``__nb``Clk2Sel_o(Fmc``__nb``Clk2Sel_o), \
.Fmc``__nb``ClkOutP_ok(Fmc``__nb``ClkOutP_ok), \
.Fmc``__nb``ClkOutN_ok(Fmc``__nb``ClkOutN_ok), \
.Fmc``__nb``Onewire_io(Fmc``__nb``Onewire_io), \
.Fmc``__nb``Led_ob(Fmc``__nb``Led_ob), \
.Fmc``__nb``Present_in(Fmc``__nb``Present_in),
hdl/svec/sim/testbench/make deleted 100644 → 0
View file @ 0ca74d29
# clean working space and compile all necessary files
# I want the HDLmake to run under Windows!
vlib work
vdel -lib work -all
vlib work
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/wishbone-gen/lib/wbgen2_pkg.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/wishbone-gen/lib/wbgen2_dpssram.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/wishbone-gen/lib/wbgen2_eic.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/wishbone-gen/lib/wbgen2_fifo_async.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/wishbone-gen/lib/wbgen2_fifo_sync.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/PulseGenerator.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/PulseGeneratorTime.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/Counter.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/CounterLength.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/ShiftRegister.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/ResetSyncer.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/Delay.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/EdgeDetector.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/ChangeDetector.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/Reg.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/RegSyncer.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/SlowToggle.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/FrequencySense.vhd
vlog -reportprogress 300 -work work ../../../ffpg/rtl/SpiMasterWb.v
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
vlog -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v
vlog -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v
vlog -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/Ad9512Control.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd
vlog -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/FfpgPkg.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/ffpg_csr_pkg.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/ffpg_csr.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/WbSlaveWrapper.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/DelayController.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/DacsController.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/DelayedPulseGenerator/Fsm.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/DelayedPulseGenerator/DelayedPulseGenerator.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/DelayedPulseGenerator/DelayedPulseGeneratorsCdc.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/Ad9512Syncer.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/FfpgSlave.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
vcom -2008 -reportprogress 300 -work work ../../../ffpg/rtl/FfpgCore.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/vme64x_pack.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_pack.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CSR_pack.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CRAM.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_IRQ_Controller.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_SharedComps.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Init.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Am_Match.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Funct_Match.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Access_Decode.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Wb_master.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_swapper.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_bus.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME64xCore_Top.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/carrier_csr.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/HeartBeat.vhd
vcom -2008 -reportprogress 300 -work work ../../rtl/SvecTopFfpg.vhd
vcom -2008 -reportprogress 300 -work work SvecTopFfpgWrapper.vhd
vlog -reportprogress 300 -work work Testbench.sv +incdir+../../../ip_cores/general-cores/sim
hdl/svec/sim/testbench/post_map deleted 100644 → 0
View file @ 0ca74d29
vcom -2008 -reportprogress 300 -work work ../../syn/netgen/map/SvecTopFfpg_map.vhd
vsim -voptargs=+acc -t ps -sdfmax /Testbench/cDut=../../syn/netgen/map/SvecTopFfpg_map.sdf work.Testbench
do res
\ No newline at end of file
hdl/svec/sim/testbench/post_par deleted 100644 → 0
View file @ 0ca74d29
vcom -2008 -reportprogress 300 -work work ../../syn/netgen/par/SvecTopFfpg_timesim.vhd
vsim -voptargs=+acc -t ps -sdfmax /Testbench/cDut=../../syn/netgen/par/SvecTopFfpg_timesim.sdf work.Testbench
do res
\ No newline at end of file
hdl/svec/sim/testbench/post_syn deleted 100644 → 0
View file @ 0ca74d29
vcom -2008 -reportprogress 300 -work work ../../syn/netgen/synthesis/SvecTopFfpg_synthesis.vhd
do res
\ No newline at end of file
hdl/svec/sim/testbench/post_tra deleted 100644 → 0
View file @ 0ca74d29
vcom -2008 -reportprogress 300 -work work ../../syn/netgen/translate/SvecTopFfpg_translate.vhd
do res
\ No newline at end of file
hdl/svec/sim/testbench/re deleted 100644 → 0
View file @ 0ca74d29
# recompile and restart with new random seed
#do make
vlog -reportprogress 300 -work work Testbench.sv +incdir+../../../ip_cores/general-cores/sim
do res
hdl/svec/sim/testbench/res deleted 100644 → 0
View file @ 0ca74d29
# restart simulation with new random seed
restart -force -sv_seed random
do run
hdl/svec/sim/testbench/run deleted 100644 → 0
View file @ 0ca74d29
set NumericStdNoWarnings 1
set StdArithNoWarnings 1
run 0 ns
set NumericStdNoWarnings 0
set StdArithNoWarnings 0
run -all
\ No newline at end of file
hdl/svec/sim/testbench/sim deleted 100644 → 0
View file @ 0ca74d29
# start simulation, set waveform, run simulation
vsim -voptargs=+acc work.Testbench
add wave -group DUT sim:/Testbench/cDut/cSvecTopFfpg/*
# add wave -group {Xbar SVEC} sim:/Testbench/cDut/cSvecTopFfpg/cWbSdbCrossbar/*
# add wave -group {Xbar FFPGCore} sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cWbSdbCrossbar/*
add wave -group FFPGCore sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/*
add wave -group FFPGSlave sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/*
# add wave -group FFPGSlave -group WbSlave sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/cWbSlaveWrapper/*
# add wave -group FFPGSlave -group DacsController sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/cDacsController/*
# add wave -group FFPGSlave -group DelayController -r sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/cDelayController/*
add wave -group FFPGSlave -group DelayedPulseGeneratorsCdc sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/*
add wave -group FFPGSlave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh1 sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh1/*
add wave -group FFPGSlave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh1 -group Fsm sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh1/cFsm/*
add wave -group FFPGSlave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh1 -group BitCounter sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh1/cBitCounter/*
add wave -group FFPGSlave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh1 -group StreamCounter sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh1/cStreamCounter/*
add wave -group FFPGSlave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh1 -group ShiftRegisterSet sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh1/cShiftRegisterSet/*
add wave -group FFPGSlave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh1 -group ShiftRegisterReset sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh1/cShiftRegisterReset/*
# add wave -group FFPGSlave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh2 sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh2/*
# add wave -group FFPGSlave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh2 -group Fsm sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh2/cFsm/*
# add wave -group FFPGSlave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh2 -group BitCounter sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh2/cBitCounter/*
# add wave -group FFPGSlave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh2 -group StreamCounter sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh2/cStreamCounter/*
# add wave -group FFPGSlave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh2 -group ShiftRegisterSet sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh2/cShiftRegisterSet/*
# add wave -group FFPGSlave -group DelayedPulseGeneratorsCdc -group DelayedPulseGeneratorCh2 -group ShiftRegisterReset sim:/Testbench/cDut/cSvecTopFfpg/cFmc0FfpgCore/cFfpgSlave/cDelayedPulseGeneratorsCdc/cDelayedPulseGeneratorCh2/cShiftRegisterReset/*
configure wave -namecolwidth 271
configure wave -valuecolwidth 100
configure wave -signalnamewidth 1
sv_reseed random
do run
wave zoomfull
hdl/svec/sim/testbench/svec_vme_buffers.svh deleted 100644 → 0
View file @ 0ca74d29
// http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw/repository/revisions/master/changes/hdl/svec/sim/vme64x_bfm/svec_vme_buffers.svh
// modified by Jan Pospisil, j.pospisil@cern.ch, 2016, CERN BE-BI-QP
`include "components/sn74vmeh22501.v"
`include "vme64x_bfm.svh"
module bidir_buf(
a,
b,
dir, /* 0: a->b, 1: b->a */
oe_n );
parameter g_width = 1;
inout [g_width-1:0] a,b;
input dir, oe_n;
assign b = (!dir && !oe_n) ? a : 'bz;
assign a = (dir && !oe_n) ? b : 'bz;
endmodule // bidir_buf
module svec_vme_buffers (
output VME_AS_n_o,
output VME_RST_n_o,
output VME_WRITE_n_o,
output [5:0] VME_AM_o,
output [1:0] VME_DS_n_o,
output [5:0] VME_GA_o,
input VME_BERR_i,
input VME_DTACK_n_i,
input VME_RETRY_n_i,
input VME_RETRY_OE_i,
inout VME_LWORD_n_b,
inout [31:1] VME_ADDR_b,
inout [31:0] VME_DATA_b,
output VME_BBSY_n_o,
input [6:0] VME_IRQ_n_i,
output VME_IACKIN_n_o,
input VME_IACKOUT_n_i,
output VME_IACK_n_o,
input VME_DTACK_OE_i,
input VME_DATA_DIR_i,
input VME_DATA_OE_N_i,
input VME_ADDR_DIR_i,
input VME_ADDR_OE_N_i,
IVME64X.slave slave
);
pullup(slave.as_n);
pullup(slave.rst_n);
pullup(slave.irq_n[0]);
pullup(slave.irq_n[1]);
pullup(slave.irq_n[2]);
pullup(slave.irq_n[3]);
pullup(slave.irq_n[4]);
pullup(slave.irq_n[5]);
pullup(slave.irq_n[6]);
pullup(slave.iack_n);
pullup(slave.dtack_n);
pullup(slave.retry_n);
pullup(slave.ds_n[1]);
pullup(slave.ds_n[0]);
pullup(slave.lword_n);
pullup(slave.berr_n);
pullup(slave.write_n);
pulldown(slave.bbsy_n);
pullup(slave.iackin_n);
assign VME_RST_n_o = slave.rst_n;
assign VME_AS_n_o = slave.as_n;
assign VME_GA_o = slave.ga;
assign VME_WRITE_n_o = slave.write_n;
assign VME_AM_o = slave.am;
assign VME_DS_n_o = slave.ds_n;
assign VME_BBSY_n_o = slave.bbsy_n;
assign VME_IACKIN_n_o = slave.iackin_n;
assign VME_IACK_n_o = slave.iack_n;
bidir_buf #(1) b0 (slave.lword_n, VME_LWORD_n_b, VME_ADDR_DIR_i, VME_ADDR_OE_N_i);
bidir_buf #(31) b1 (slave.addr, VME_ADDR_b, VME_ADDR_DIR_i, VME_ADDR_OE_N_i);
bidir_buf #(32) b2 (slave.data, VME_DATA_b, VME_DATA_DIR_i, VME_DATA_OE_N_i);
pulldown(VME_BERR_i);
pulldown(VME_ADDR_DIR_i);
pulldown(VME_ADDR_OE_N_i);
pulldown(VME_DATA_DIR_i);
pulldown(VME_DATA_OE_N_i);
assign slave.dtack_n = VME_DTACK_n_i;
assign slave.berr_n = ~VME_BERR_i;
assign slave.retry_n = VME_RETRY_n_i;
endmodule
`define DECLARE_VME_BUFFERS(iface) \
wire VME_AS_n;\
wire VME_RST_n;\
wire VME_WRITE_n;\
wire [5:0] VME_AM;\
wire [1:0] VME_DS_n;\
wire VME_BERR;\
wire VME_DTACK_n;\
wire VME_RETRY_n;\
wire VME_RETRY_OE;\
wire VME_LWORD_n;\
wire [31:1]VME_ADDR;\
wire [31:0]VME_DATA;\
wire VME_BBSY_n;\
wire [6:0]VME_IRQ_n;\
wire VME_IACKIN_n,VME_IACK_n;\
wire VME_IACKOUT_n;\
wire VME_DTACK_OE;\
wire VME_DATA_DIR;\
wire VME_DATA_OE_N;\
wire VME_ADDR_DIR;\
wire VME_ADDR_OE_N;\
svec_vme_buffers U_VME_Bufs ( \
.VME_AS_n_o(VME_AS_n),\
.VME_RST_n_o(VME_RST_n),\
.VME_WRITE_n_o(VME_WRITE_n),\
.VME_AM_o(VME_AM),\
.VME_DS_n_o(VME_DS_n),\
.VME_GA_o(),\
.VME_BERR_i(VME_BERR),\
.VME_DTACK_n_i(VME_DTACK_n),\
.VME_RETRY_n_i(VME_RETRY_n),\
.VME_RETRY_OE_i(VME_RETRY_OE),\
.VME_LWORD_n_b(VME_LWORD_n),\
.VME_ADDR_b(VME_ADDR),\
.VME_DATA_b(VME_DATA),\
.VME_BBSY_n_o(),\
.VME_IRQ_n_i(VME_IRQ_n),\
.VME_IACK_n_o(VME_IACK_n),\
.VME_IACKIN_n_o(VME_IACKIN_n),\
.VME_IACKOUT_n_i(VME_IACKOUT_n),\
.VME_DTACK_OE_i(VME_DTACK_OE),\
.VME_DATA_DIR_i(VME_DATA_DIR),\
.VME_DATA_OE_N_i(VME_DATA_OE_N),\
.VME_ADDR_DIR_i(VME_ADDR_DIR),\
.VME_ADDR_OE_N_i(VME_ADDR_OE_N),\
.slave(iface)\
);
function automatic bit[5:0] _gen_ga(int slot);
bit[4:0] slot_id = slot;
return {^slot_id, ~slot_id};
endfunction // _gen_ga
`define WIRE_VME_PINS(slot_id) \
.VmeAs_n_i(VME_AS_n),\
.VmeSysreset_n_i(VME_RST_n),\
.VmeWrite_n_i(VME_WRITE_n),\
.VmeAm_i(VME_AM),\
.VmeDs_n_i(VME_DS_n),\
.VmeGa_i(_gen_ga(slot_id)),\
.VmeBerr_o(VME_BERR),\
.VmeDtack_n_o(VME_DTACK_n),\
.VmeRetry_n_o(VME_RETRY_n),\
.VmeRetry_oe_o(VME_RETRY_OE),\
.VmeLword_n_b(VME_LWORD_n),\
.VmeAddr_b(VME_ADDR),\
.VmeData_b(VME_DATA),\
.VmeIrq_n_o(VME_IRQ_n),\
.VmeIack_n_i(VME_IACK_n),\
.VmeIackin_n_i(VME_IACKIN_n),\
.VmeIackout_n_o(VME_IACKOUT_n),\
.VmeDtack_oe_o(VME_DTACK_OE),\
.VmeData_dir_o(VME_DATA_DIR),\
.VmeData_oe_n_o(VME_DATA_OE_N),\
.VmeAddr_dir_o(VME_ADDR_DIR),\
.VmeAddr_oe_n_o(VME_ADDR_OE_N)
hdl/svec/sim/testbench/vme64x_bfm.svh deleted 100644 → 0
View file @ 0ca74d29
// http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw/repository/revisions/master/changes/hdl/svec/sim/vme64x_bfm/vme64x_bfm.svh
// modified by Jan Pospisil, j.pospisil@cern.ch, 2016, CERN BE-BI-QP
`ifndef __VME64X_BFM_SVH
`define __VME64X_BFM_SVH 1
`timescale 1ns/1ps
`include "simdrv_defs.svh"
`define assert_wait(name, condition, timeout) \
begin\
time t=$time;\
while(!(condition)) begin\
#1ns;\
if($time - t > timeout) begin\
$display("Wait timeout : ", `"name`"); \
// $stop;\
break;\
end\
end\
end
interface IVME64X ( input sys_rst_n_i );
wire as_n;
wire rst_n;
wire write_n;
wire [5:0] am;
wire [1:0] ds_n;
wire [5:0] ga;
wire berr_n, dtack_n;
wire retry_n;
wire lword_n;
wire [31:1] addr;
wire [31:0] data;
wire bbsy_n;
wire [6:0] irq_n;
wire iackin_n, iackout_n, iack_n;
logic q_as_n = 1'bz;
logic q_rst_n = 1'bz;
logic q_write_n = 1'bz;
logic [5:0] q_am = 6'bz;
logic [1:0] q_ds_n = 2'bz;
logic [5:0] q_ga = 6'bz;
logic q_berr_n = 1'bz, q_dtack_n = 1'bz;
logic q_retry_n = 1'bz;
logic q_lword_n = 1'bz;
logic [31:1] q_addr = 31'bz;
logic [31:0] q_data = 32'bz;
logic q_bbsy_n = 1'bz;
logic [6:0] q_irq_n = 7'bz;
logic q_iackin_n = 1'bz, q_iackout_n = 1'bz, q_iack_n = 1'bz;
/* SystemVerilog does not allow pullups inside interfaces or on logic type */
assign as_n = q_as_n;
assign rst_n = q_rst_n;
assign write_n = q_write_n;
assign am = q_am;
assign ds_n = q_ds_n;
assign ga = q_ga;
assign berr_n = q_berr_n;
assign dtack_n = q_dtack_n;
assign retry_n = q_retry_n;
assign lword_n = q_lword_n;
assign addr = q_addr;
assign data = q_data;
assign bbsy_n = q_bbsy_n;
assign irq_n = q_irq_n;
assign iackin_n = q_iackin_n;
assign iackout_n = q_iackout_n;
assign iack_n = q_iack_n;
// VME Master
modport tb
(
output as_n,
output rst_n,
output write_n,
output am,
output ds_n,
output ga,
output bbsy_n,
output iackin_n,
output iack_n,
input berr_n,
input irq_n,
input iackout_n,
inout addr,
inout data,
inout lword_n,
inout retry_n,
inout dtack_n,
input q_as_n,
input q_rst_n,
input q_write_n,
input q_am,
input q_ds_n,
input q_ga,
input q_bbsy_n,
input q_iackin_n,
input q_iack_n,
input q_berr_n,
input q_irq_n,
input q_iackout_n,
input q_addr,
input q_data,
input q_lword_n,
input q_retry_n,
input q_dtack_n
);
modport master
(
output as_n,
output rst_n,
output write_n,
output am,
output ds_n,
output ga,
output bbsy_n,
output iackin_n,
output iack_n,
input berr_n,
input irq_n,
input iackout_n,
inout addr,
inout data,
inout lword_n,
inout retry_n,
inout dtack_n);
// VME Slave
modport slave
(
input as_n,
input rst_n,
input write_n,
input am,
input ds_n,
input ga,
input bbsy_n,
input iackin_n,
input iack_n,
output berr_n,
output irq_n,
output iackout_n,
inout addr,
inout data,
inout lword_n,
inout retry_n,
inout dtack_n
);
initial forever begin
@(posedge sys_rst_n_i);
#100ns;
q_rst_n = 0;
#100ns;
q_rst_n = 1;
end
endinterface // IVME64x
const uint64_t CSR_BAR = 'h7FFFF;
const uint64_t CSR_BIT_SET_REG = 'h7FFFB;
const uint64_t CSR_BIT_CLR_REG = 'h7FFF7;
const uint64_t CSR_CRAM_OWNER = 'h7FFF3;
const uint64_t CSR_USR_BIT_SET_REG = 'h7FFEF;
const uint64_t CSR_USR_BIT_CLR_REG = 'h7FFEB;
typedef enum { DONT_CARE = 'h100,
A16 = 'h200,
A24 = 'h300,
A32 = 'h400,
A64 = 'h500
} vme_addr_size_t;
typedef enum {
SINGLE = 'h10, CR_CSR='h20, MBLT='h30, BLT='h40, LCK='h50, TwoeVME='h60, TwoeSST='h70 } vme_xfer_type_t;
typedef enum { D08Byte0='h1, D08Byte1='h2, D08Byte2='h3, D08Byte3='h4, D16Byte01='h5, D16Byte23='h6, D32='h7 } vme_data_type_t ;
class CBusAccessor_VME64x extends CBusAccessor;
const bit [3:0] dt_map [vme_data_type_t] =
'{
D08Byte0 : 4'b0101,
D08Byte1 : 4'b1001,
D08Byte2 : 4'b0111,
D08Byte3 : 4'b1011,
D16Byte01 : 4'b0001,
D16Byte23 : 4'b0011,
D32 : 4'b0000};
protected bit [7:0] m_ba;
protected bit [4:0] m_ga;
virtual IVME64X.tb vme;
function new(virtual IVME64X.tb _vme);
vme = _vme;
m_ga = 6'b010111;
vme.q_ga = m_ga;
m_ba = 8'b10000000;
endfunction // new
protected task set_address(uint64_t addr_in, vme_addr_size_t asize, vme_xfer_type_t xtype);
bit[63:0] a = addr_in;
bit [31:0] a_out;
const bit [5:0] am_map [int] =
'{
A32 | CR_CSR : 6'b101111,
A24 | CR_CSR : 6'b101111,
A16 | SINGLE: 6'b101001,
A16 | LCK : 6'b101100,
A24 | SINGLE: 6'b111001,
A24 | BLT : 6'b111011,
A24 | MBLT : 6'b111000,
A24 | LCK : 6'b110010,
A32 | SINGLE: 6'b001001,
A32 | BLT : 6'b001011,
A32 | MBLT : 6'b001000,
A32 | LCK : 6'b000101,
A64 | SINGLE: 6'b000001,
A64 | BLT : 6'b000011,
A64 | MBLT : 6'b000000,
A64 | LCK : 6'b001000,
A32 | TwoeVME : 6'b100000,
A64 | TwoeVME : 6'b100000,
A32 | TwoeSST : 6'b100000,
A64 | TwoeSST : 6'b100000};
vme.q_am = am_map[asize|xtype];
if(xtype == CR_CSR)
a_out = {8'h0, ~m_ga[4:0], a[18:0]};
else case(asize)
A16:
a_out = {16'h0, m_ba[7:3], a[10:2], 2'b00};
A24:
a_out = {8'h0, m_ba[7:3], a[18:2], 2'b00};
A32:
a_out = {m_ba[7:3], a[26:2], 2'b00};
endcase // case (xtype)
vme.q_addr[31:2] = a_out[31:2];
endtask // set_address
protected task release_bus();
vme.q_as_n = 1'bz;
vme.q_write_n = 1'bz;
vme.q_ds_n = 2'bzz;
vme.q_lword_n = 1'bz;
vme.q_addr = 0;
vme.q_data = 32'bz;
endtask // release_bus
/* Simple generic VME read/write: single, BLT and CSR xfers */
protected task rw_generic(bit write, uint64_t _addr, ref uint64_t _data[], input vme_addr_size_t asize, input vme_xfer_type_t xtype, vme_data_type_t dtype);
bit[3:0] dt;
int i;
`assert_wait(tmo_rws_bus_free, vme.dtack_n && vme.berr_n, 10us)
release_bus();
#10ns;
set_address(_addr, asize, xtype);
dt = dt_map[dtype];
vme.q_lword_n = dt[0];
vme.q_addr[1] = dt[1];
vme.q_write_n = !write;
#35ns;
vme.q_as_n = 0;
#10ns;
// $display("RWG %x\n", _data.size());
for(i=0;i<_data.size();i++)
begin
if(write)
vme.q_data = (dtype == D08Byte0 || dtype == D08Byte2) ? (_data[i] << 8) : (_data[i]);
#35ns;
vme.q_ds_n = dt[3:2];
`assert_wait(tmo_rws_bus_idle, !vme.dtack_n || !vme.berr_n, 4us)
if(!vme.berr_n)
$error("[rw_simple_generic]: VME bus error.");
if(!write && !vme.dtack_n)
_data[i] = (dtype == D08Byte0 || dtype == D08Byte2) ? (vme.data >> 8) : (vme.data);
else
_data[i] = -1; // invalid read
#10ns;
end // for (i=0;i<_data.size();i++)
release_bus();
endtask // rw_generic
protected task extract_xtype(int s, ref vme_xfer_type_t xtype, vme_addr_size_t asize, vme_data_type_t dtype);
xtype = vme_xfer_type_t'( s & 'h0f0);
asize = vme_addr_size_t'( s & 'hf00);
dtype = vme_data_type_t'( s & 'h00f);
endtask // extract_xtype
protected int m_default_modifiers = A32 | SINGLE | D32;
task set_default_modifiers(int mods);
m_default_modifiers = mods;
endtask // set_default_modifiers
task writem(uint64_t addr[], uint64_t data[], input int size = m_default_modifiers, ref int result);
int i;
vme_addr_size_t asize;
vme_data_type_t dtype;
vme_xfer_type_t xtype;
extract_xtype(size, xtype, asize, dtype);
if(xtype == SINGLE || xtype == CR_CSR)
for(i=0;i<addr.size();i++)
begin
uint64_t tmp[];
tmp = new[1];
tmp[0] = data[i];
rw_generic(1, addr[i], tmp, asize, xtype, dtype);
end
else if (xtype == BLT)
rw_generic(1, addr[0], data, asize, xtype, dtype);
endtask // writem
task readm(uint64_t addr[], ref uint64_t data[], input int size = m_default_modifiers, ref int result);
int i;
vme_addr_size_t asize;
vme_data_type_t dtype;
vme_xfer_type_t xtype;
extract_xtype(size, xtype, asize, dtype);
if(xtype == SINGLE || xtype == CR_CSR)
for(i=0;i<addr.size();i++)
begin
uint64_t tmp[];
tmp=new[1];
rw_generic(0, addr[i], tmp, asize, xtype, dtype);
data[i] = tmp[0];
end
endtask // readm
task read(uint64_t addr, ref uint64_t data, input int size = m_default_modifiers, ref int result = _null);
int res;
uint64_t aa[1], da[];
da= new[1];
aa[0] = addr;
readm(aa, da, size, res);
data = da[0];
endtask
task write(uint64_t addr, uint64_t data, input int size = m_default_modifiers, ref int result = _null);
uint64_t aa[], da[];
aa=new[1];
da=new[1];
// $display("VMEWrite s %x", size);
aa[0] = addr;
da[0] = data;
writem(aa, da, size, result);
endtask
endclass // CBusAccessor_VME64x
`endif // `ifndef __VME64X_BFM_SVH
hdl/svec/syn/SvecFfpg.xise deleted 100644 → 0
View file @ 0ca74d29
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<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other VCOM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VLOG Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VSIM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="SvecTopFfpg" xil_pn:valueState="default"/>
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<property xil_pn:name="Package" xil_pn:value="fgg900" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
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<property xil_pn:name="Project Description" xil_pn:value="http://www.ohwr.org/projects/fmc-del-1ns-2cha/" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
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<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="SvecTopFfpgWrapper" xil_pn:valueState="non-default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Simulator" xil_pn:value="Modelsim-SE Mixed" xil_pn:valueState="non-default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Modelsim-SE Mixed" xil_pn:valueState="default"/>
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<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Automatic Do File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Configuration Name" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Explicit Declarations Only" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-200X" xil_pn:valueState="non-default"/>
<property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/>
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<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="true" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="SvecTopFfpg" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-07-26T14:29:00" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="6D3B358E90AC486696A212F22B7240E4" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
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<files>
<file xil_pn:name="../rtl/SvecTopFfpg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
</file>
<file xil_pn:name="../../ffpg/rtl/FfpgCore.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="71"/>
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<file xil_pn:name="../../ffpg/rtl/FfpgSlave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
</file>
<file xil_pn:name="../../ffpg/rtl/DacsController.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
</file>
<file xil_pn:name="../../ffpg/rtl/DelayController.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
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<file xil_pn:name="../../ffpg/rtl/WbSlaveWrapper.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
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<file xil_pn:name="../../ffpg/rtl/DelayedPulseGenerator/DelayedPulseGenerator.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ffpg/rtl/DelayedPulseGenerator/DelayedPulseGeneratorFsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
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<file xil_pn:name="../../ffpg/rtl/Counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
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<file xil_pn:name="../../ffpg/rtl/Delay.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
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<file xil_pn:name="../../ffpg/rtl/RegSyncer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
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<file xil_pn:name="../../ffpg/rtl/ShiftRegister.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
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<file xil_pn:name="../../ffpg/rtl/ResetSyncer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
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<bindings>
<binding xil_pn:location="/SvecTopFfpg" xil_pn:name="SvecFfpg.ucf"/>
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<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
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hdl/svec/wb_gen/Makefile deleted 100644 → 0
View file @ 0ca74d29
WBGEN2=wbgen2
RTL=../rtl/
DOC=../../../doc/manual/svec/
SIM=../sim/testbench/
%:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $(DOC)$@.htm -C $@.h -K $(SIM)$@.svh $@.wb
hdl/svec/wb_gen/carrier_csr.h deleted 100644 → 0
View file @ 0ca74d29
/*
Register definitions for slave core: SVEC carrier control and status registers
* File : carrier_csr.h
* Author : auto-generated by wbgen2 from carrier_csr.wb
* Created : 12/19/16 17:04:37
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_CARRIER_CSR_WB
#define __WBGEN2_REGDEFS_CARRIER_CSR_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1ULL<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Carrier type and PCB version */
/* definitions for field: PCB revision in reg: Carrier type and PCB version */
#define CARRIER_CSR_CARRIER_PCB_REV_MASK WBGEN2_GEN_MASK(0, 5)
#define CARRIER_CSR_CARRIER_PCB_REV_SHIFT 0
#define CARRIER_CSR_CARRIER_PCB_REV_W(value) WBGEN2_GEN_WRITE(value, 0, 5)
#define CARRIER_CSR_CARRIER_PCB_REV_R(reg) WBGEN2_GEN_READ(reg, 0, 5)
/* definitions for field: Reserved register in reg: Carrier type and PCB version */
#define CARRIER_CSR_CARRIER_RESERVED_MASK WBGEN2_GEN_MASK(5, 11)
#define CARRIER_CSR_CARRIER_RESERVED_SHIFT 5
#define CARRIER_CSR_CARRIER_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 5, 11)
#define CARRIER_CSR_CARRIER_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 5, 11)
/* definitions for field: Carrier type in reg: Carrier type and PCB version */
#define CARRIER_CSR_CARRIER_TYPE_MASK WBGEN2_GEN_MASK(16, 16)
#define CARRIER_CSR_CARRIER_TYPE_SHIFT 16
#define CARRIER_CSR_CARRIER_TYPE_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define CARRIER_CSR_CARRIER_TYPE_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Status */
/* definitions for field: FMC 1 presence in reg: Status */
#define CARRIER_CSR_STAT_FMC0_PRES WBGEN2_GEN_MASK(0, 1)
/* definitions for field: FMC 2 presence in reg: Status */
#define CARRIER_CSR_STAT_FMC1_PRES WBGEN2_GEN_MASK(1, 1)
/* definitions for field: System clock PLL status in reg: Status */
#define CARRIER_CSR_STAT_SYS_PLL_LCK WBGEN2_GEN_MASK(2, 1)
/* definitions for field: NOT_IMPLEMENTED: DDR3 bank 4 calibration status in reg: Status */
#define CARRIER_CSR_STAT_DDR0_CAL_DONE WBGEN2_GEN_MASK(3, 1)
/* definitions for field: NOT_IMPLEMENTED: DDR3 bank 5 calibration status in reg: Status */
#define CARRIER_CSR_STAT_DDR1_CAL_DONE WBGEN2_GEN_MASK(4, 1)
/* definitions for register: Control */
/* definitions for field: NOT_IMPLEMENTED: Front panel LED manual control in reg: Control */
#define CARRIER_CSR_CTRL_FP_LEDS_MAN_MASK WBGEN2_GEN_MASK(0, 16)
#define CARRIER_CSR_CTRL_FP_LEDS_MAN_SHIFT 0
#define CARRIER_CSR_CTRL_FP_LEDS_MAN_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define CARRIER_CSR_CTRL_FP_LEDS_MAN_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: Reset Register */
/* definitions for field: State of the FMC 1 reset line in reg: Reset Register */
#define CARRIER_CSR_RST_FMC0_N WBGEN2_GEN_MASK(0, 1)
/* definitions for field: State of the FMC 2 reset line in reg: Reset Register */
#define CARRIER_CSR_RST_FMC1_N WBGEN2_GEN_MASK(1, 1)
PACKED struct CARRIER_CSR_WB {
/* [0x0]: REG Carrier type and PCB version */
uint32_t CARRIER;
/* [0x4]: REG Status */
uint32_t STAT;
/* [0x8]: REG Control */
uint32_t CTRL;
/* [0xc]: REG Reset Register */
uint32_t RST;
};
#define CARRIER_CSR_PERIPH_PREFIX "carrier_csr"
#define CARRIER_CSR_PERIPH_NAME "SVEC carrier control and status registers"
#define CARRIER_CSR_PERIPH_DESC WBGEN2_DESC("Wishbone slave for control and status registers related to the SVEC FMC carrier")
#endif
hdl/svec/wb_gen/carrier_csr.wb deleted 100644 → 0
View file @ 0ca74d29
peripheral {
name = "SVEC carrier control and status registers";
description = "Wishbone slave for control and status registers related to the SVEC FMC carrier";
hdl_entity = "carrier_csr";
prefix = "carrier_csr";
reg {
name = "Carrier type and PCB version";
prefix = "carrier";
field {
name = "PCB revision";
description = "Binary coded PCB layout revision.";
prefix = "pcb_rev";
type = SLV;
size = 5;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Reserved register";
description = "Ignore on read, write with 0's.";
prefix = "reserved";
type = SLV;
size = 11;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Carrier type";
description = "Carrier type identifier\n1 = SPEC\n2 = SVEC\n3 = VFC\n4 = SPEXI";
prefix = "type";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Status";
prefix = "stat";
field {
name = "FMC 1 presence";
description = "0: FMC slot 1 is populated\n1: FMC slot 1 is not populated.";
prefix = "fmc0_pres";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "FMC 2 presence";
description = "0: FMC slot 2 is populated\n1: FMC slot 2 is not populated.";
prefix = "fmc1_pres";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "System clock PLL status";
description = "0: not locked\n1: locked.";
prefix = "sys_pll_lck";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "NOT_IMPLEMENTED: DDR3 bank 4 calibration status";
description = "0: not done\n1: done.";
prefix = "ddr0_cal_done";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "NOT_IMPLEMENTED: DDR3 bank 5 calibration status";
description = "0: not done\n1: done.";
prefix = "ddr1_cal_done";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Control";
prefix = "ctrl";
field {
name = "NOT_IMPLEMENTED: Front panel LED manual control";
description = "NOT_IMPLEMENTED: Height front panel LED, two bits per LED.\n00 = OFF\n01 = Green\n10 = Red\n11 = Orange";
prefix = "fp_leds_man";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Reset Register";
prefix = "rst";
description = "Controls software reset of the mezzanines including the ddr interface and the time-tagging core.";
field {
name = "State of the FMC 1 reset line";
description = "write 0: FMC is held in reset\
write 1: Normal FMC operation (default)";
type = BIT;
load = LOAD_EXT;
size = 1;
prefix = "fmc0_n";
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
field {
name = "State of the FMC 2 reset line";
description = "write 0: FMC is held in reset\
write 1: Normal FMC operation (default)";
type = BIT;
load = LOAD_EXT;
size = 1;
prefix = "fmc1_n";
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
};
hdl/syn/svec/.gitignore 0 → 100644
View file @ a3dc2ea8
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
*
!.gitignore
!Manifest.py
!*.ucf
!syn_extra_steps.tcl
hdl/syn/svec/Manifest.py 0 → 100644
View file @ a3dc2ea8
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: LGPL-2.1-or-later
board = "svec"
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900"
syn_top = "svec_top_ffpg"
syn_project = "svec_top_ffpg.xise"
syn_tool = "ise"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
files = [
"buildinfo_pkg.vhd",
"sourceid_{}_pkg.vhd".format(syn_top),
"svec_top_ffpg.ucf",
]
# Ideally this should be done by hdlmake itself, to allow downstream Manifests to be able to use the
# fetchto variable independent of where those Manifests reside in the filesystem.
# However, this needs to happen after the files section above, otherwise the two ucf files from the
# dependency will not be taken into account!!!
import os
fetchto = os.path.abspath(fetchto)
modules = {
"local" : [
"../../top/svec",
],
}
try:
exec(open(fetchto + "/general-cores/tools/gen_sourceid.py").read(),
None, {'project': syn_top})
except Exception as e:
print("Error: cannot generate source id file")
raise
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
svec_base_ucf = ['led', 'gpio']
ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
hdl/svec/syn/SvecFfpg.ucf → hdl/syn/svec/svec_top_ffpg.ucf
View file @ a3dc2ea8
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CERN-OHL-W-2.0+
#===============================================================================
# The IO Location Constraints
#===============================================================================
#----------------------------------------
# Clock and reset inputs
#----------------------------------------
NET "Clk20_ik" LOC = V26;
# NET "clk_125m_pllref_n_i" LOC = AB30;
# NET "clk_125m_pllref_p_i" LOC = AB28;
NET "Clk20_ik" IOSTANDARD = "LVCMOS33";
# NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
# NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "Reset_inr" LOC = AD28;
NET "Reset_inr" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Clock controls
#----------------------------------------
NET "Pll20DacDin_o" LOC = U28;
NET "Pll20DacSclk_o" LOC = AA28;
NET "Pll20DacSync_on" LOC = N28;
NET "Pll25DacDin_o" LOC = P25;
NET "Pll25DacSclk_o" LOC = N27;
NET "Pll25DacSync_on" LOC = P26;
NET "Pll20DacDin_o" IOSTANDARD = "LVCMOS33";
NET "Pll20DacSclk_o" IOSTANDARD = "LVCMOS33";
NET "Pll20DacSync_on" IOSTANDARD = "LVCMOS33";
NET "Pll25DacDin_o" IOSTANDARD = "LVCMOS33";
NET "Pll25DacSclk_o" IOSTANDARD = "LVCMOS33";
NET "Pll25DacSync_on" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Front panel LEDs & LEMOs
#----------------------------------------
NET "FpLedsLineEnable_ob2[0]" LOC = AD26;
NET "FpLedsLineEnable_ob2[1]" LOC = AD27;
NET "FpLedsLine_ob2[0]" LOC = AC27;
NET "FpLedsLine_ob2[1]" LOC = AC28;
NET "FpLedsColumn_ob4[0]" LOC = AE30;
NET "FpLedsColumn_ob4[1]" LOC = AE27;
NET "FpLedsColumn_ob4[2]" LOC = AE28;
NET "FpLedsColumn_ob4[3]" LOC = AF28;
NET "FpLedsLineEnable_ob2[0]" IOSTANDARD="LVCMOS33";
NET "FpLedsLineEnable_ob2[1]" IOSTANDARD="LVCMOS33";
NET "FpLedsLine_ob2[0]" IOSTANDARD="LVCMOS33";
NET "FpLedsLine_ob2[1]" IOSTANDARD="LVCMOS33";
NET "FpLedsColumn_ob4[0]" IOSTANDARD="LVCMOS33";
NET "FpLedsColumn_ob4[1]" IOSTANDARD="LVCMOS33";
NET "FpLedsColumn_ob4[2]" IOSTANDARD="LVCMOS33";
NET "FpLedsColumn_ob4[3]" IOSTANDARD="LVCMOS33";
NET "FpLemo_ob4[1]" LOC = T28;
NET "FpLemo_ob4[2]" LOC = R30;
NET "FpLemo_ob4[3]" LOC = V27;
NET "FpLemo_ob4[4]" LOC = U29;
NET "FpLemo_ob4[1]" IOSTANDARD="LVCMOS33";
NET "FpLemo_ob4[2]" IOSTANDARD="LVCMOS33";
NET "FpLemo_ob4[3]" IOSTANDARD="LVCMOS33";
NET "FpLemo_ob4[4]" IOSTANDARD="LVCMOS33";
NET "FpLemoDir1_A2B_o" LOC = T30;
NET "FpLemoDir2_A2B_o" LOC = R29;
NET "FpLemoDir34_A2B_o" LOC = V28;
NET "FpLemoDir1_A2B_o" IOSTANDARD="LVCMOS33";
NET "FpLemoDir2_A2B_o" IOSTANDARD="LVCMOS33";
NET "FpLemoDir34_A2B_o" IOSTANDARD="LVCMOS33";
NET "FpLemoTerm_oeb4[1]" LOC = AB1;
NET "FpLemoTerm_oeb4[2]" LOC = W5;
NET "FpLemoTerm_oeb4[3]" LOC = W4;
NET "FpLemoTerm_oeb4[4]" LOC = V4;
NET "FpLemoTerm_oeb4[1]" IOSTANDARD="LVCMOS33";
NET "FpLemoTerm_oeb4[2]" IOSTANDARD="LVCMOS33";
NET "FpLemoTerm_oeb4[3]" IOSTANDARD="LVCMOS33";
NET "FpLemoTerm_oeb4[4]" IOSTANDARD="LVCMOS33";
#----------------------------------------
# Carrier I2C EEPROM
#----------------------------------------
NET "CarrierScl_io" LOC = AC29;
NET "CarrierSda_io" LOC = AA30;
NET "CarrierScl_io" IOSTANDARD = "LVCMOS33";
NET "CarrierSda_io" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# PCB revision
#----------------------------------------
NET "PcbRev_i[4]" LOC = AF17;
NET "PcbRev_i[3]" LOC = AE17;
NET "PcbRev_i[2]" LOC = AD18;
NET "PcbRev_i[1]" LOC = AE20;
NET "PcbRev_i[0]" LOC = AD20;
NET "PcbRev_i[4]" IOSTANDARD = "LVCMOS25";
NET "PcbRev_i[3]" IOSTANDARD = "LVCMOS25";
NET "PcbRev_i[2]" IOSTANDARD = "LVCMOS25";
NET "PcbRev_i[1]" IOSTANDARD = "LVCMOS25";
NET "PcbRev_i[0]" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# 1-wire thermoeter + unique ID
#----------------------------------------
NET "CarrierOneWire_io" LOC = AC30;
NET "CarrierOneWire_io" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# VME interface
#----------------------------------------
NET "VmeWrite_n_i" LOC = R1;
NET "VmeSysreset_n_i" LOC = P4;
# NET "VmeSysclk_i" LOC = P3;
NET "VmeRetry_oe_o" LOC = R4;
NET "VmeRetry_n_o" LOC = AB2;
NET "VmeLword_n_b" LOC = M7;
NET "VmeIackout_n_o" LOC = N3;
NET "VmeIackin_n_i" LOC = P7;
NET "VmeIack_n_i" LOC = N1;
NET "VmeDtack_oe_o" LOC = T1;
NET "VmeDtack_n_o" LOC = R5;
NET "VmeDs_n_i[1]" LOC = Y7;
NET "VmeDs_n_i[0]" LOC = Y6;
NET "VmeData_oe_n_o" LOC = P1;
NET "VmeData_dir_o" LOC = P2;
NET "VmeBerr_o" LOC = R3;
NET "VmeAs_n_i" LOC = P6;
NET "VmeAddr_oe_n_o" LOC = N4;
NET "VmeAddr_dir_o" LOC = N5;
NET "VmeIrq_n_o[7]" LOC = R7;
NET "VmeIrq_n_o[6]" LOC = AH2;
NET "VmeIrq_n_o[5]" LOC = AF2;
NET "VmeIrq_n_o[4]" LOC = N9;
NET "VmeIrq_n_o[3]" LOC = N10;
NET "VmeIrq_n_o[2]" LOC = AH4;
NET "VmeIrq_n_o[1]" LOC = AG4;
NET "VmeGa_i[5]" LOC = M6;
NET "VmeGa_i[4]" LOC = V9;
NET "VmeGa_i[3]" LOC = V10;
NET "VmeGa_i[2]" LOC = AJ1;
NET "VmeGa_i[1]" LOC = AH1;
NET "VmeGa_i[0]" LOC = V7;
NET "VmeData_b[31]" LOC = AK3;
NET "VmeData_b[30]" LOC = AH3;
NET "VmeData_b[29]" LOC = T8;
NET "VmeData_b[28]" LOC = T9;
NET "VmeData_b[27]" LOC = AK4;
NET "VmeData_b[26]" LOC = AJ4;
NET "VmeData_b[25]" LOC = W6;
NET "VmeData_b[24]" LOC = W7;
NET "VmeData_b[23]" LOC = AB6;
NET "VmeData_b[22]" LOC = AB7;
NET "VmeData_b[21]" LOC = W9;
NET "VmeData_b[20]" LOC = W10;
NET "VmeData_b[19]" LOC = AK5;
NET "VmeData_b[18]" LOC = AH5;
NET "VmeData_b[17]" LOC = AD6;
NET "VmeData_b[16]" LOC = AC6;
NET "VmeData_b[15]" LOC = AA6;
NET "VmeData_b[14]" LOC = AA7;
NET "VmeData_b[13]" LOC = T6;
NET "VmeData_b[12]" LOC = T7;
NET "VmeData_b[11]" LOC = AG5;
NET "VmeData_b[10]" LOC = AE5;
NET "VmeData_b[9]" LOC = Y11;
NET "VmeData_b[8]" LOC = W11;
NET "VmeData_b[7]" LOC = AF6;
NET "VmeData_b[6]" LOC = AE6;
NET "VmeData_b[5]" LOC = Y8;
NET "VmeData_b[4]" LOC = Y9;
NET "VmeData_b[3]" LOC = AE7;
NET "VmeData_b[2]" LOC = AD7;
NET "VmeData_b[1]" LOC = AA9;
NET "VmeData_b[0]" LOC = AA10;
NET "VmeAm_i[5]" LOC = V8;
NET "VmeAm_i[4]" LOC = AG3;
NET "VmeAm_i[3]" LOC = AF3;
NET "VmeAm_i[2]" LOC = AF4;
NET "VmeAm_i[1]" LOC = AE4;
NET "VmeAm_i[0]" LOC = AK2;
NET "VmeAddr_b[31]" LOC = T2;
NET "VmeAddr_b[30]" LOC = T3;
NET "VmeAddr_b[29]" LOC = T4;
NET "VmeAddr_b[28]" LOC = U1;
NET "VmeAddr_b[27]" LOC = U3;
NET "VmeAddr_b[26]" LOC = U4;
NET "VmeAddr_b[25]" LOC = U5;
NET "VmeAddr_b[24]" LOC = V1;
NET "VmeAddr_b[23]" LOC = V2;
NET "VmeAddr_b[22]" LOC = W1;
NET "VmeAddr_b[21]" LOC = W3;
NET "VmeAddr_b[20]" LOC = AA4;
NET "VmeAddr_b[19]" LOC = AA5;
NET "VmeAddr_b[18]" LOC = Y1;
NET "VmeAddr_b[17]" LOC = Y2;
NET "VmeAddr_b[16]" LOC = Y3;
NET "VmeAddr_b[15]" LOC = Y4;
NET "VmeAddr_b[14]" LOC = AC1;
NET "VmeAddr_b[13]" LOC = AC3;
NET "VmeAddr_b[12]" LOC = AD1;
NET "VmeAddr_b[11]" LOC = AD2;
NET "VmeAddr_b[10]" LOC = AB3;
NET "VmeAddr_b[9]" LOC = AB4;
NET "VmeAddr_b[8]" LOC = AD3;
NET "VmeAddr_b[7]" LOC = AD4;
NET "VmeAddr_b[6]" LOC = AC4;
NET "VmeAddr_b[5]" LOC = AC5;
NET "VmeAddr_b[4]" LOC = N7;
NET "VmeAddr_b[3]" LOC = N8;
NET "VmeAddr_b[2]" LOC = AE1;
NET "VmeAddr_b[1]" LOC = AE3;
NET "VmeWrite_n_i" IOSTANDARD = "LVCMOS33";
NET "VmeSysreset_n_i" IOSTANDARD = "LVCMOS33";
# NET "VmeSysclk_i" IOSTANDARD = "LVCMOS33";
NET "VmeRetry_oe_o" IOSTANDARD = "LVCMOS33";
NET "VmeRetry_n_o" IOSTANDARD = "LVCMOS33";
NET "VmeLword_n_b" IOSTANDARD = "LVCMOS33";
NET "VmeIackout_n_o" IOSTANDARD = "LVCMOS33";
NET "VmeIackin_n_i" IOSTANDARD = "LVCMOS33";
NET "VmeIack_n_i" IOSTANDARD = "LVCMOS33";
NET "VmeDtack_oe_o" IOSTANDARD = "LVCMOS33";
NET "VmeDtack_n_o" IOSTANDARD = "LVCMOS33";
NET "VmeDs_n_i[1]" IOSTANDARD = "LVCMOS33";
NET "VmeDs_n_i[0]" IOSTANDARD = "LVCMOS33";
NET "VmeData_oe_n_o" IOSTANDARD = "LVCMOS33";
NET "VmeData_dir_o" IOSTANDARD = "LVCMOS33";
NET "VmeBerr_o" IOSTANDARD = "LVCMOS33";
NET "VmeAs_n_i" IOSTANDARD = "LVCMOS33";
NET "VmeAddr_oe_n_o" IOSTANDARD = "LVCMOS33";
NET "VmeAddr_dir_o" IOSTANDARD = "LVCMOS33";
NET "VmeIrq_n_o[7]" IOSTANDARD = "LVCMOS33";
NET "VmeIrq_n_o[6]" IOSTANDARD = "LVCMOS33";
NET "VmeIrq_n_o[5]" IOSTANDARD = "LVCMOS33";
NET "VmeIrq_n_o[4]" IOSTANDARD = "LVCMOS33";
NET "VmeIrq_n_o[3]" IOSTANDARD = "LVCMOS33";
NET "VmeIrq_n_o[2]" IOSTANDARD = "LVCMOS33";
NET "VmeIrq_n_o[1]" IOSTANDARD = "LVCMOS33";
NET "VmeGa_i[5]" IOSTANDARD = "LVCMOS33";
NET "VmeGa_i[4]" IOSTANDARD = "LVCMOS33";
NET "VmeGa_i[3]" IOSTANDARD = "LVCMOS33";
NET "VmeGa_i[2]" IOSTANDARD = "LVCMOS33";
NET "VmeGa_i[1]" IOSTANDARD = "LVCMOS33";
NET "VmeGa_i[0]" IOSTANDARD = "LVCMOS33";
NET "VmeData_b[31]" IOSTANDARD = "LVCMOS33";
NET "VmeData_b[30]" IOSTANDARD = "LVCMOS33";
NET "VmeData_b[29]" IOSTANDARD = "LVCMOS33";
NET "VmeData_b[28]" IOSTANDARD = "LVCMOS33";
NET "VmeData_b[27]" IOSTANDARD = "LVCMOS33";
NET "VmeData_b[26]" IOSTANDARD = "LVCMOS33";
NET "VmeData_b[25]" IOSTANDARD = "LVCMOS33";
NET "VmeData_b[24]" IOSTANDARD = "LVCMOS33";
NET "VmeData_b[23]" IOSTANDARD = "LVCMOS33";
NET "VmeData_b[22]" IOSTANDARD = "LVCMOS33";
NET "VmeData_b[21]" IOSTANDARD = "LVCMOS33";
NET "VmeData_b[20]" IOSTANDARD = "LVCMOS33";
NET "VmeData_b[19]" IOSTANDARD = "LVCMOS33";
NET "VmeData_b[18]" IOSTANDARD = "LVCMOS33";
NET "VmeData_b[17]" IOSTANDARD = "LVCMOS33";
NET "VmeData_b[16]" IOSTANDARD = "LVCMOS33";
NET "VmeData_b[15]" IOSTANDARD = "LVCMOS33";
NET "VmeData_b[14]" IOSTANDARD = "LVCMOS33";
NET "VmeData_b[13]" IOSTANDARD = "LVCMOS33";
NET "VmeData_b[12]" IOSTANDARD = "LVCMOS33";
NET "VmeData_b[11]" IOSTANDARD = "LVCMOS33";
NET "VmeData_b[10]" IOSTANDARD = "LVCMOS33";
NET "VmeData_b[9]" IOSTANDARD = "LVCMOS33";
NET "VmeData_b[8]" IOSTANDARD = "LVCMOS33";
NET "VmeData_b[7]" IOSTANDARD = "LVCMOS33";
NET "VmeData_b[6]" IOSTANDARD = "LVCMOS33";
NET "VmeData_b[5]" IOSTANDARD = "LVCMOS33";
NET "VmeData_b[4]" IOSTANDARD = "LVCMOS33";
NET "VmeData_b[3]" IOSTANDARD = "LVCMOS33";
NET "VmeData_b[2]" IOSTANDARD = "LVCMOS33";
NET "VmeData_b[1]" IOSTANDARD = "LVCMOS33";
NET "VmeData_b[0]" IOSTANDARD = "LVCMOS33";
NET "VmeAm_i[5]" IOSTANDARD = "LVCMOS33";
NET "VmeAm_i[4]" IOSTANDARD = "LVCMOS33";
NET "VmeAm_i[3]" IOSTANDARD = "LVCMOS33";
NET "VmeAm_i[2]" IOSTANDARD = "LVCMOS33";
NET "VmeAm_i[1]" IOSTANDARD = "LVCMOS33";
NET "VmeAm_i[0]" IOSTANDARD = "LVCMOS33";
NET "VmeAddr_b[31]" IOSTANDARD = "LVCMOS33";
NET "VmeAddr_b[30]" IOSTANDARD = "LVCMOS33";
NET "VmeAddr_b[29]" IOSTANDARD = "LVCMOS33";
NET "VmeAddr_b[28]" IOSTANDARD = "LVCMOS33";
NET "VmeAddr_b[27]" IOSTANDARD = "LVCMOS33";
NET "VmeAddr_b[26]" IOSTANDARD = "LVCMOS33";
NET "VmeAddr_b[25]" IOSTANDARD = "LVCMOS33";
NET "VmeAddr_b[24]" IOSTANDARD = "LVCMOS33";
NET "VmeAddr_b[23]" IOSTANDARD = "LVCMOS33";
NET "VmeAddr_b[22]" IOSTANDARD = "LVCMOS33";
NET "VmeAddr_b[21]" IOSTANDARD = "LVCMOS33";
NET "VmeAddr_b[20]" IOSTANDARD = "LVCMOS33";
NET "VmeAddr_b[19]" IOSTANDARD = "LVCMOS33";
NET "VmeAddr_b[18]" IOSTANDARD = "LVCMOS33";
NET "VmeAddr_b[17]" IOSTANDARD = "LVCMOS33";
NET "VmeAddr_b[16]" IOSTANDARD = "LVCMOS33";
NET "VmeAddr_b[15]" IOSTANDARD = "LVCMOS33";
NET "VmeAddr_b[14]" IOSTANDARD = "LVCMOS33";
NET "VmeAddr_b[13]" IOSTANDARD = "LVCMOS33";
NET "VmeAddr_b[12]" IOSTANDARD = "LVCMOS33";
NET "VmeAddr_b[11]" IOSTANDARD = "LVCMOS33";
NET "VmeAddr_b[10]" IOSTANDARD = "LVCMOS33";
NET "VmeAddr_b[9]" IOSTANDARD = "LVCMOS33";
NET "VmeAddr_b[8]" IOSTANDARD = "LVCMOS33";
NET "VmeAddr_b[7]" IOSTANDARD = "LVCMOS33";
NET "VmeAddr_b[6]" IOSTANDARD = "LVCMOS33";
NET "VmeAddr_b[5]" IOSTANDARD = "LVCMOS33";
NET "VmeAddr_b[4]" IOSTANDARD = "LVCMOS33";
NET "VmeAddr_b[3]" IOSTANDARD = "LVCMOS33";
NET "VmeAddr_b[2]" IOSTANDARD = "LVCMOS33";
NET "VmeAddr_b[1]" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# FMC slots management
#----------------------------------------
NET "Fmc0Present_in" LOC = N30;
# NET "Fmc0Scl" LOC = P28;
# NET "Fmc0Sda" LOC = P30;
NET "Fmc0Present_in" IOSTANDARD = "LVCMOS33";
# NET "Fmc0Scl" IOSTANDARD = "LVCMOS33";
# NET "Fmc0Sda" IOSTANDARD = "LVCMOS33";
NET "Fmc1Present_in" LOC = AE29;
# NET "Fmc1Scl" LOC = W29;
# NET "Fmc1Sda" LOC = V30;
NET "Fmc1Present_in" IOSTANDARD = "LVCMOS33";
# NET "Fmc1Scl" IOSTANDARD = "LVCMOS33";
# NET "Fmc1Sda" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# FMC slot 0
#----------------------------------------
......@@ -676,11 +358,6 @@ NET "Fmc1SpiAd9512Cs_on" IOSTANDARD = "LVCMOS25";
# Timing constraints
#===============================================================================
# System clock
NET "Clk20_ik" TNM_NET = tmn_Clk20_ik;
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "tmn_Clk20_ik" 50 ns HIGH 50%;
# RF clock
NET "Fmc0ClkIn0P_ik" TNM_NET = tmn_Fmc0ClkIn0P_ik;
......@@ -698,8 +375,4 @@ TIMESPEC TS_Fmc1MultiCycle = FROM tmn_Fmc1ClkIn0P_ik TO PADS TS_Fmc1ClkIn0P_ik*3
#===============================================================================
# Reset
#NET "powerup_rst_n" TIG;
#NET "sw_rst_fmc0_n" TIG;
#NET "sw_rst_fmc1_n" TIG;
# add top level resets here? and what about CDC in DelayedPulseGenerator.vhd ?
hdl/syn/svec/syn_extra_steps.tcl 0 → 100644
View file @ a3dc2ea8
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: LGPL-2.1-or-later
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
hdl/top/svec/Manifest.py 0 → 100644
View file @ a3dc2ea8
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: LGPL-2.1-or-later
files = [
"svec_top_ffpg.vhd",
"svec_top_ffpg_map.vhd",
]
modules = {
"local" : [
"../../ffpg/rtl",
"../../ip_cores/svec",
"../../ip_cores/general-cores",
"../../ip_cores/vme64x-core",
"../../ip_cores/ddr3-sp6-core",
"../../ip_cores/wr-cores",
],
#"git" : [
# "https://ohwr.org/project/svec.git",
# "https://ohwr.org/project/general-cores.git",
# "https://ohwr.org/project/vme64x-core.git",
#],
}
hdl/top/svec/svec_top_ffpg.vhd 0 → 100644
View file @ a3dc2ea8
-------------------------------------------------------------------------------
-- Title : Top-level entity for implementation on SVEC carrier card
-- Project : FMC DEL 1ns 2cha (FFPG)
-- URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
-------------------------------------------------------------------------------
-- File : svec_top_ffpg.vhd
-- Author(s) : Jan Pospisil <j.pospisil@cern.ch>
-- Company : CERN (BE-BI-QP)
-- Created : 2016-07-26
-- Last update: 2023-02-23
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Contains code for two FMC mezzanines, communication via VME bus
-- and other board specific code.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CERN (BE-BI-QP)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Comment
-- 2016-08-24 1.0 Jan Pospisil
-- 2023-02-23 2.0 Tom Levens Port to new SVEC reference design
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
use work.wishbone_pkg.all;
use work.gencores_pkg.all;
use work.wr_board_pkg.all;
use work.wr_fabric_pkg.all;
use work.FfpgPkg.all;
use work.sourceid_svec_top_ffpg_pkg;
library unisim;
use unisim.vcomponents.all;
entity svec_top_ffpg is
generic (
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_SIMULATION : integer := 0;
-- Increase information messages during simulation
g_VERBOSE : boolean := False
);
port (
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
-- Reset from system fpga
rst_n_i : in std_logic;
-- 125 MHz PLL reference
clk_125m_pllref_p_i : in std_logic;
clk_125m_pllref_n_i : in std_logic;
-- 20MHz VCXO clock (for WR)
clk_20m_vcxo_i : in std_logic := '0';
-- 125 MHz GTP reference
clk_125m_gtp_n_i : in std_logic := '0';
clk_125m_gtp_p_i : in std_logic := '0';
---------------------------------------------------------------------------
-- VME interface
---------------------------------------------------------------------------
vme_write_n_i : in std_logic;
vme_sysreset_n_i : in std_logic;
vme_retry_oe_o : out std_logic;
vme_retry_n_o : out std_logic;
vme_lword_n_b : inout std_logic;
vme_iackout_n_o : out std_logic;
vme_iackin_n_i : in std_logic;
vme_iack_n_i : in std_logic;
vme_gap_i : in std_logic;
vme_dtack_oe_o : out std_logic;
vme_dtack_n_o : out std_logic;
vme_ds_n_i : in std_logic_vector(1 downto 0);
vme_data_oe_n_o : out std_logic;
vme_data_dir_o : out std_logic;
vme_berr_o : out std_logic;
vme_as_n_i : in std_logic;
vme_addr_oe_n_o : out std_logic;
vme_addr_dir_o : out std_logic;
vme_irq_o : out std_logic_vector(7 downto 1);
vme_ga_i : in std_logic_vector(4 downto 0);
vme_data_b : inout std_logic_vector(31 downto 0);
vme_am_i : in std_logic_vector(5 downto 0);
vme_addr_b : inout std_logic_vector(31 downto 1);
---------------------------------------------------------------------------
-- FMC interface
---------------------------------------------------------------------------
-- I2C interface for accessing FMC EEPROM.
fmc0_scl_b : inout std_logic;
fmc0_sda_b : inout std_logic;
fmc1_scl_b : inout std_logic;
fmc1_sda_b : inout std_logic;
-- Presence (there is a pull-up)
fmc0_prsnt_m2c_n_i: in std_logic;
fmc1_prsnt_m2c_n_i: in std_logic;
---------------------------------------------------------------------------
-- Carrier
---------------------------------------------------------------------------
-- Onewire interface
onewire_b : inout std_logic;
-- Carrier I2C eeprom
carrier_scl_b : inout std_logic;
carrier_sda_b : inout std_logic;
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
spi_sclk_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic;
---------------------------------------------------------------------------
-- SPI interface to DACs
---------------------------------------------------------------------------
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
pll20dac_din_o : out std_logic;
pll20dac_sclk_o : out std_logic;
pll20dac_sync_n_o : out std_logic;
pll25dac_din_o : out std_logic;
pll25dac_sclk_o : out std_logic;
pll25dac_sync_n_o : out std_logic;
---------------------------------------------------------------------------
-- SFP I/O for transceiver
---------------------------------------------------------------------------
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic := '0';
sfp_rxn_i : in std_logic := '0';
sfp_mod_def0_i : in std_logic := '0'; -- sfp detect
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic := '0';
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic := '0';
---------------------------------------------------------------------------
-- FMC slot 0
---------------------------------------------------------------------------
-- clock
Fmc0ClkIn0P_ik: in std_logic;
Fmc0ClkIn0N_ik: in std_logic;
-- DACs
Fmc0TriggerDac_o: out t_Ad5600Interface;
Fmc0VcxoDac_o: out t_Ad5600Interface;
-- output enable
Fmc0Ch1OutputEnable_o: out std_logic;
Fmc0Ch2OutputEnable_o: out std_logic;
-- signal feedback
Fmc0Ch1OutCal_i: in std_logic;
Fmc0Ch2OutCal_i: in std_logic;
-- delay configuration
Fmc0DelayValue_ob: out unsigned(9 downto 0);
Fmc0Ch1SetLe_on: out std_logic;
Fmc0Ch1ResLe_on: out std_logic;
Fmc0Ch2SetLe_on: out std_logic;
Fmc0Ch2ResLe_on: out std_logic;
Fmc0Ch1SetP_o: out std_logic;
Fmc0Ch1SetN_o: out std_logic;
Fmc0Ch1ResP_o: out std_logic;
Fmc0Ch1ResN_o: out std_logic;
Fmc0Ch2SetP_o: out std_logic;
Fmc0Ch2SetN_o: out std_logic;
Fmc0Ch2ResP_o: out std_logic;
Fmc0Ch2ResN_o: out std_logic;
Fmc0TriggerP_i: in std_logic;
Fmc0TriggerN_i: in std_logic;
-- AD9512 SPI
Fmc0SpiAd9512Sclk_o: out std_logic;
Fmc0SpiAd9512Mosi_o: out std_logic;
Fmc0SpiAd9512Miso_i: in std_logic;
Fmc0SpiAd9512Cs_on: out std_logic;
-- AD9512 func. pin
Fmc0Ad9512Func_o: out std_logic;
-- clock selection pin of SY58017U
Fmc0Clk2Sel_o: out std_logic;
-- clock output
Fmc0ClkOutP_ok: out std_logic;
Fmc0ClkOutN_ok: out std_logic;
-- temperature chip interface
Fmc0Onewire_io: inout std_logic;
-- LEDs
Fmc0Led_ob: out std_logic_vector(4 downto 1);
---------------------------------------------------------------------------
-- FMC slot 1
---------------------------------------------------------------------------
-- clock
Fmc1ClkIn0P_ik: in std_logic;
Fmc1ClkIn0N_ik: in std_logic;
-- DACs
Fmc1TriggerDac_o: out t_Ad5600Interface;
Fmc1VcxoDac_o: out t_Ad5600Interface;
-- output enable
Fmc1Ch1OutputEnable_o: out std_logic;
Fmc1Ch2OutputEnable_o: out std_logic;
-- signal feedback
Fmc1Ch1OutCal_i: in std_logic;
Fmc1Ch2OutCal_i: in std_logic;
-- delay configuration
Fmc1DelayValue_ob: out unsigned(9 downto 0);
Fmc1Ch1SetLe_on: out std_logic;
Fmc1Ch1ResLe_on: out std_logic;
Fmc1Ch2SetLe_on: out std_logic;
Fmc1Ch2ResLe_on: out std_logic;
Fmc1Ch1SetP_o: out std_logic;
Fmc1Ch1SetN_o: out std_logic;
Fmc1Ch1ResP_o: out std_logic;
Fmc1Ch1ResN_o: out std_logic;
Fmc1Ch2SetP_o: out std_logic;
Fmc1Ch2SetN_o: out std_logic;
Fmc1Ch2ResP_o: out std_logic;
Fmc1Ch2ResN_o: out std_logic;
Fmc1TriggerP_i: in std_logic;
Fmc1TriggerN_i: in std_logic;
-- AD9512 SPI
Fmc1SpiAd9512Sclk_o: out std_logic;
Fmc1SpiAd9512Mosi_o: out std_logic;
Fmc1SpiAd9512Miso_i: in std_logic;
Fmc1SpiAd9512Cs_on: out std_logic;
-- AD9512 func. pin
Fmc1Ad9512Func_o: out std_logic;
-- clock selection pin of SY58017U
Fmc1Clk2Sel_o: out std_logic;
-- clock output
Fmc1ClkOutP_ok: out std_logic;
Fmc1ClkOutN_ok: out std_logic;
-- temperature chip interface
Fmc1Onewire_io: inout std_logic;
-- LEDs
Fmc1Led_ob: out std_logic_vector(4 downto 1);
---------------------------------------------------------------------------
-- General
---------------------------------------------------------------------------
-- PCB revision
pcbrev_i : in std_logic_vector(4 downto 0);
-- Carrier front panel LEDs
fp_led_line_oen_o : out std_logic_vector(1 downto 0);
fp_led_line_o : out std_logic_vector(1 downto 0);
fp_led_column_o : out std_logic_vector(3 downto 0);
-- GPIO
fp_gpio1_b : in std_logic;
fp_gpio2_b : in std_logic;
fp_gpio3_b : in std_logic;
fp_gpio4_b : in std_logic;
fp_term_en_o : out std_logic_vector(4 downto 1);
fp_gpio1_a2b_o : out std_logic;
fp_gpio2_a2b_o : out std_logic;
fp_gpio34_a2b_o : out std_logic
);
end entity svec_top_ffpg;
architecture top of svec_top_ffpg is
-- Clocks & reset
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
-- Wishbone
signal master_wb_out : t_wishbone_master_out;
signal master_wb_in : t_wishbone_master_in;
signal metadata_wb_out, ffpg0_wb_out, ffpg1_wb_out : t_wishbone_slave_out;
signal metadata_wb_in, ffpg0_wb_in, ffpg1_wb_in : t_wishbone_slave_in;
-- For differential inputs
signal Fmc0ClkIn0_k, Fmc0Trigger : std_logic;
signal Fmc1ClkIn0_k, Fmc1Trigger : std_logic;
-- For differentials outputs
signal Fmc0Ch1Set, Fmc0Ch1Res, Fmc0Ch2Set, Fmc0Ch2Res : std_logic;
signal Fmc0ClkOutDdr, Fmc0ClkOut_k : std_logic;
signal Fmc1Ch1Set, Fmc1Ch1Res, Fmc1Ch2Set, Fmc1Ch2Res : std_logic;
signal Fmc1ClkOutDdr, Fmc1ClkOut_k : std_logic;
-- Front panel LED control
signal led_state : std_logic_vector(15 downto 0);
signal vme_access : std_logic;
signal fp_gpio_in : std_logic_vector(4 downto 1);
signal fp_gpio : std_logic_vector(4 downto 1);
signal fp_gpio_led : std_logic_vector(4 downto 1);
begin
cmp_svec_top_ffpg_map : entity work.svec_top_ffpg_map
port map (
rst_n_i => rst_sys_62m5_n,
clk_i => clk_sys_62m5,
wb_i => master_wb_out,
wb_o => master_wb_in,
metadata_i => metadata_wb_out,
metadata_o => metadata_wb_in,
ffpg0_i => ffpg0_wb_out,
ffpg0_o => ffpg0_wb_in,
ffpg1_i => ffpg1_wb_out,
ffpg1_o => ffpg1_wb_in
);
cmp_xwb_metadata : entity work.xwb_metadata
generic map (
g_VENDOR_ID => x"0000_10DC",
g_DEVICE_ID => x"465047_01", -- FPG_01,
g_VERSION => sourceid_svec_top_ffpg_pkg.version,
g_CAPABILITIES => x"0000_0000",
g_COMMIT_ID => sourceid_svec_top_ffpg_pkg.sourceid
)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
wb_i => metadata_wb_in,
wb_o => metadata_wb_out
);
inst_svec_base: entity work.svec_base_wr
generic map (
g_with_vic => False,
g_with_onewire => True,
g_with_spi => True,
g_with_wr => False,
g_with_ddr4 => False,
g_with_ddr5 => False,
g_app_offset => x"0000_4000",
g_num_user_irq => 0,
g_dpram_initf => "",
g_fabric_iface => open,
g_streamers_op_mode => open,
g_tx_streamer_params => open,
g_rx_streamer_params => open,
g_simulation => g_SIMULATION,
g_verbose => g_VERBOSE
)
port map (
rst_n_i => rst_n_i,
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
vme_write_n_i => vme_write_n_i,
vme_sysreset_n_i => vme_sysreset_n_i,
vme_retry_oe_o => vme_retry_oe_o,
vme_retry_n_o => vme_retry_n_o,
vme_lword_n_b => vme_lword_n_b,
vme_iackout_n_o => vme_iackout_n_o,
vme_iackin_n_i => vme_iackin_n_i,
vme_iack_n_i => vme_iack_n_i,
vme_gap_i => vme_gap_i,
vme_dtack_oe_o => vme_dtack_oe_o,
vme_dtack_n_o => vme_dtack_n_o,
vme_ds_n_i => vme_ds_n_i,
vme_data_oe_n_o => vme_data_oe_n_o,
vme_data_dir_o => vme_data_dir_o,
vme_berr_o => vme_berr_o,
vme_as_n_i => vme_as_n_i,
vme_addr_oe_n_o => vme_addr_oe_n_o,
vme_addr_dir_o => vme_addr_dir_o,
vme_irq_o => vme_irq_o,
vme_ga_i => vme_ga_i,
vme_data_b => vme_data_b,
vme_am_i => vme_am_i,
vme_addr_b => vme_addr_b,
fmc0_scl_b => fmc0_scl_b,
fmc0_sda_b => fmc0_sda_b,
fmc1_scl_b => fmc1_scl_b,
fmc1_sda_b => fmc1_sda_b,
fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
fmc1_prsnt_m2c_n_i => fmc1_prsnt_m2c_n_i,
onewire_b => onewire_b,
carrier_scl_b => carrier_scl_b,
carrier_sda_b => carrier_sda_b,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
plldac_sclk_o => plldac_sclk_o,
plldac_din_o => plldac_din_o,
pll20dac_din_o => pll20dac_din_o,
pll20dac_sclk_o => pll20dac_sclk_o,
pll20dac_sync_n_o => pll20dac_sync_n_o,
pll25dac_din_o => pll25dac_din_o,
pll25dac_sclk_o => pll25dac_sclk_o,
pll25dac_sync_n_o => pll25dac_sync_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_mod_def0_i => sfp_mod_def0_i,
sfp_mod_def1_b => sfp_mod_def1_b,
sfp_mod_def2_b => sfp_mod_def2_b,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
ddr4_a_o => open,
ddr4_ba_o => open,
ddr4_cas_n_o => open,
ddr4_ck_n_o => open,
ddr4_ck_p_o => open,
ddr4_cke_o => open,
ddr4_dq_b => open,
ddr4_ldm_o => open,
ddr4_ldqs_n_b => open,
ddr4_ldqs_p_b => open,
ddr4_odt_o => open,
ddr4_ras_n_o => open,
ddr4_reset_n_o => open,
ddr4_rzq_b => open,
ddr4_udm_o => open,
ddr4_udqs_n_b => open,
ddr4_udqs_p_b => open,
ddr4_we_n_o => open,
ddr5_a_o => open,
ddr5_ba_o => open,
ddr5_cas_n_o => open,
ddr5_ck_n_o => open,
ddr5_ck_p_o => open,
ddr5_cke_o => open,
ddr5_dq_b => open,
ddr5_ldm_o => open,
ddr5_ldqs_n_b => open,
ddr5_ldqs_p_b => open,
ddr5_odt_o => open,
ddr5_ras_n_o => open,
ddr5_reset_n_o => open,
ddr5_rzq_b => open,
ddr5_udm_o => open,
ddr5_udqs_n_b => open,
ddr5_udqs_p_b => open,
ddr5_we_n_o => open,
pcbrev_i => pcbrev_i,
ddr4_clk_i => clk_sys_62m5,
ddr4_rst_n_i => rst_sys_62m5_n,
ddr4_wb_i.cyc => '0',
ddr4_wb_i.stb => '0',
ddr4_wb_i.adr => x"0000_0000",
ddr4_wb_i.sel => x"00",
ddr4_wb_i.we => '0',
ddr4_wb_i.dat => (63 downto 0 => '0'),
ddr4_wb_o => open,
ddr5_clk_i => clk_sys_62m5,
ddr5_rst_n_i => rst_sys_62m5_n,
ddr5_wb_i.cyc => '0',
ddr5_wb_i.stb => '0',
ddr5_wb_i.adr => x"0000_0000",
ddr5_wb_i.sel => x"00",
ddr5_wb_i.we => '0',
ddr5_wb_i.dat => (63 downto 0 => '0'),
ddr5_wb_o => open,
ddr4_wr_fifo_empty_o => open,
ddr5_wr_fifo_empty_o => open,
clk_sys_62m5_o => clk_sys_62m5,
rst_sys_62m5_n_o => rst_sys_62m5_n,
clk_ref_125m_o => open,
rst_ref_125m_n_o => open,
irq_user_i => "",
wrf_src_o => open,
wrf_src_i => open,
wrf_snk_o => open,
wrf_snk_i => open,
wrs_tx_data_i => open,
wrs_tx_valid_i => open,
wrs_tx_dreq_o => open,
wrs_tx_last_i => open,
wrs_tx_flush_i => open,
wrs_tx_cfg_i => open,
wrs_rx_first_o => open,
wrs_rx_last_o => open,
wrs_rx_data_o => open,
wrs_rx_valid_o => open,
wrs_rx_dreq_i => open,
wrs_rx_cfg_i => open,
wb_eth_master_o => open,
wb_eth_master_i => open,
tm_link_up_o => open,
tm_time_valid_o => open,
tm_tai_o => open,
tm_cycles_o => open,
pps_p_o => open,
pps_led_o => open,
link_ok_o => open,
led_link_o => open,
led_act_o => open,
app_wb_o => master_wb_out,
app_wb_i => master_wb_in
);
------------------------------------------------------------------------------
-- Carrier front panel LEDs and LEMOs
------------------------------------------------------------------------------
cmp_led_controller : entity work.gc_bicolor_led_ctrl
generic map (
g_nb_column => 4,
g_nb_line => 2,
g_clk_freq => 62500000, -- in Hz
g_refresh_rate => 250 -- in Hz
)
port map (
rst_n_i => rst_sys_62m5_n,
clk_i => clk_sys_62m5,
led_intensity_i => "1100100", -- in %
led_state_i => led_state,
column_o => fp_led_column_o,
line_o => fp_led_line_o,
line_oen_o => fp_led_line_oen_o
);
cmp_vme_access_led : gc_extend_pulse
generic map (
g_width => 2500000
)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
pulse_i => master_wb_out.stb,
extended_o => vme_access
);
-- LED order on front panel (top to bottom)
-- 7-6 5-4 3-2 1-0
-- 15-14 13-12 11-10 9-8
led_state(1 downto 0) <= c_led_green when vme_access = '1' else c_led_off;
led_state(3 downto 2) <= c_led_off;
led_state(5 downto 4) <= c_led_off;
led_state(7 downto 6) <= c_led_off;
led_state(9 downto 8) <= c_led_green when fp_gpio_led(4) = '1' else c_led_off;
led_state(11 downto 10) <= c_led_green when fp_gpio_led(3) = '1' else c_led_off;
led_state(13 downto 12) <= c_led_green when fp_gpio_led(2) = '1' else c_led_off;
led_state(15 downto 14) <= c_led_green when fp_gpio_led(1) = '1' else c_led_off;
-- Front panel IO configuration
fp_term_en_o <= (others => '0');
fp_gpio1_a2b_o <= '0';
fp_gpio2_a2b_o <= '0';
fp_gpio34_a2b_o <= '0';
fp_gpio_in(1) <= fp_gpio1_b;
fp_gpio_in(2) <= fp_gpio2_b;
fp_gpio_in(3) <= fp_gpio3_b;
fp_gpio_in(4) <= fp_gpio4_b;
-- Front panel IO synchronisation
gen_fp_gpio_sync: for i in 1 to 4 generate
begin
cmp_fp_gpio_sync: gc_sync_ffs
port map (
clk_i => clk_sys_62m5,
rst_n_i => '1',
data_i => fp_gpio_in(i),
ppulse_o => fp_gpio(i)
);
cmp_fp_gpio_led : gc_extend_pulse
generic map (
g_width => 2500000
)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
pulse_i => fp_gpio(i),
extended_o => fp_gpio_led(i)
);
end generate;
-----------------------------------------------------------------------------
-- FMC slot 0 - FFPG
-----------------------------------------------------------------------------
cFmc0ClkIn0Ibufgds: IBUFGDS
generic map (
DIFF_TERM => TRUE
)
port map (
I => Fmc0ClkIn0P_ik,
IB => Fmc0ClkIn0N_ik,
O => Fmc0ClkIn0_k
);
cFmc0TriggerIbufds: IBUFDS
generic map (
DIFF_TERM => TRUE
)
port map (
I => Fmc0TriggerP_i,
IB => Fmc0TriggerN_i,
O => Fmc0Trigger
);
cFmc0FfpgCore: entity work.FfpgCore(syn)
generic map (
g_ClkFrequency => 62500000 -- in Hz
)
port map (
-- Wishbone connection
Clk_ik => clk_sys_62m5,
Reset_ira => not rst_sys_62m5_n,
Wb_i => ffpg0_wb_in,
Wb_o => ffpg0_wb_out,
---- FMC interface
-- clock
ClkIn0_ik => Fmc0ClkIn0_k,
-- DACs
TriggerDac_o => Fmc0TriggerDac_o,
VcxoDac_o => Fmc0VcxoDac_o,
-- output enable
Ch1OutputEnable_o => Fmc0Ch1OutputEnable_o,
Ch2OutputEnable_o => Fmc0Ch2OutputEnable_o,
-- delay configuration
DelayValue_ob => Fmc0DelayValue_ob,
Ch1SetLe_on => Fmc0Ch1SetLe_on,
Ch1ResLe_on => Fmc0Ch1ResLe_on,
Ch2SetLe_on => Fmc0Ch2SetLe_on,
Ch2ResLe_on => Fmc0Ch2ResLe_on,
Ch1Set_o => Fmc0Ch1Set,
Ch1Res_o => Fmc0Ch1Res,
Ch2Set_o => Fmc0Ch2Set,
Ch2Res_o => Fmc0Ch2Res,
Trigger_i => Fmc0Trigger,
-- AD9512 SPI
SpiAd9512Sclk_o => Fmc0SpiAd9512Sclk_o,
SpiAd9512Mosi_o => Fmc0SpiAd9512Mosi_o,
SpiAd9512Miso_i => Fmc0SpiAd9512Miso_i,
SpiAd9512Cs_on => Fmc0SpiAd9512Cs_on,
-- AD9512 func. pin
Ad9512Func_o => Fmc0Ad9512Func_o,
-- clock selection pin of SY58017U
Clk2Sel_o => Fmc0Clk2Sel_o,
-- clock output
ClkOut_ok => Fmc0ClkOut_k,
-- temperature chip interface
Onewire_io => Fmc0Onewire_io,
-- LEDs
Led_ob => Fmc0Led_ob
);
cFmc0Ch1SetObufds: OBUFDS
port map (
I => Fmc0Ch1Set,
O => Fmc0Ch1SetP_o,
OB => Fmc0Ch1SetN_o
);
cFmc0Ch1ResObufds: OBUFDS
port map (
I => Fmc0Ch1Res,
O => Fmc0Ch1ResP_o,
OB => Fmc0Ch1ResN_o
);
cFmc0Ch2SetObufds: OBUFDS
port map (
I => Fmc0Ch2Set,
O => Fmc0Ch2SetP_o,
OB => Fmc0Ch2SetN_o
);
cFmc0Ch2ResObufds: OBUFDS
port map (
I => Fmc0Ch2Res,
O => Fmc0Ch2ResP_o,
OB => Fmc0Ch2ResN_o
);
cFmc0ClkOutOddr: ODDR2
generic map (
DDR_ALIGNMENT => "C0",
SRTYPE => "ASYNC"
)
port map (
Q => Fmc0ClkOutDdr,
C0 => Fmc0ClkOut_k,
C1 => not Fmc0ClkOut_k,
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0'
);
cFmc0ClkOutObufds: OBUFDS
port map (
I => Fmc0ClkOutDdr,
O => Fmc0ClkOutP_ok,
OB => Fmc0ClkOutN_ok
);
-----------------------------------------------------------------------------
-- FMC slot 1 - FFPG
-----------------------------------------------------------------------------
cFmc1ClkIn0Ibufgds: IBUFGDS
generic map (
DIFF_TERM => TRUE
)
port map (
I => Fmc1ClkIn0P_ik,
IB => Fmc1ClkIn0N_ik,
O => Fmc1ClkIn0_k
);
cFmc1TriggerIbufds: IBUFDS
generic map (
DIFF_TERM => TRUE
)
port map (
I => Fmc1TriggerP_i,
IB => Fmc1TriggerN_i,
O => Fmc1Trigger
);
cFmc1FfpgCore: entity work.FfpgCore(syn)
generic map (
g_ClkFrequency => 62500000 -- in Hz
)
port map (
-- Wishbone connection
Clk_ik => clk_sys_62m5,
Reset_ira => not rst_sys_62m5_n,
Wb_i => ffpg1_wb_in,
Wb_o => ffpg1_wb_out,
---- FMC interface
-- clock
ClkIn0_ik => Fmc1ClkIn0_k,
-- DACs
TriggerDac_o => Fmc1TriggerDac_o,
VcxoDac_o => Fmc1VcxoDac_o,
-- output enable
Ch1OutputEnable_o => Fmc1Ch1OutputEnable_o,
Ch2OutputEnable_o => Fmc1Ch2OutputEnable_o,
-- delay configuration
DelayValue_ob => Fmc1DelayValue_ob,
Ch1SetLe_on => Fmc1Ch1SetLe_on,
Ch1ResLe_on => Fmc1Ch1ResLe_on,
Ch2SetLe_on => Fmc1Ch2SetLe_on,
Ch2ResLe_on => Fmc1Ch2ResLe_on,
Ch1Set_o => Fmc1Ch1Set,
Ch1Res_o => Fmc1Ch1Res,
Ch2Set_o => Fmc1Ch2Set,
Ch2Res_o => Fmc1Ch2Res,
Trigger_i => Fmc1Trigger,
-- AD9512 SPI
SpiAd9512Sclk_o => Fmc1SpiAd9512Sclk_o,
SpiAd9512Mosi_o => Fmc1SpiAd9512Mosi_o,
SpiAd9512Miso_i => Fmc1SpiAd9512Miso_i,
SpiAd9512Cs_on => Fmc1SpiAd9512Cs_on,
-- AD9512 func. pin
Ad9512Func_o => Fmc1Ad9512Func_o,
-- clock selection pin of SY58017U
Clk2Sel_o => Fmc1Clk2Sel_o,
-- clock output
ClkOut_ok => Fmc1ClkOut_k,
-- temperature chip interface
Onewire_io => Fmc1Onewire_io,
-- LEDs
Led_ob => Fmc1Led_ob
);
cFmc1Ch1SetObufds: OBUFDS
port map (
I => Fmc1Ch1Set,
O => Fmc1Ch1SetP_o,
OB => Fmc1Ch1SetN_o
);
cFmc1Ch1ResObufds: OBUFDS
port map (
I => Fmc1Ch1Res,
O => Fmc1Ch1ResP_o,
OB => Fmc1Ch1ResN_o
);
cFmc1Ch2SetObufds: OBUFDS
port map (
I => Fmc1Ch2Set,
O => Fmc1Ch2SetP_o,
OB => Fmc1Ch2SetN_o
);
cFmc1Ch2ResObufds: OBUFDS
port map (
I => Fmc1Ch2Res,
O => Fmc1Ch2ResP_o,
OB => Fmc1Ch2ResN_o
);
cFmc1ClkOutOddr: ODDR2
generic map (
DDR_ALIGNMENT => "C0",
SRTYPE => "ASYNC"
)
port map (
Q => Fmc1ClkOutDdr,
C0 => Fmc1ClkOut_k,
C1 => not Fmc1ClkOut_k,
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0'
);
cFmc1ClkOutObufds: OBUFDS
port map (
I => Fmc1ClkOutDdr,
O => Fmc1ClkOutP_ok,
OB => Fmc1ClkOutN_ok
);
end architecture top;
hdl/top/svec/svec_top_ffpg_map.cheby 0 → 100644
View file @ a3dc2ea8
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: CC-BY-SA-4.0+ OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
memory-map:
name: svec_top_ffpg_map
bus: wb-32-be
size: 0x80000
x-hdl:
busgroup: True
children:
- submap:
name: metadata
description: a ROM containing the carrier metadata
address: 0x4000
size: 0x40
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: ffpg0
description: FFPG core 0
address: 0x20000
size: 0x20000
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: ffpg1
description: FFPG core 1
address: 0x60000
size: 0x20000
interface: wb-32-be
x-hdl:
busgroup: True
hdl/top/svec/svec_top_ffpg_map.vhd 0 → 100644
View file @ a3dc2ea8
-- Do not edit. Generated by cheby 1.6.dev0 using these options:
-- -i svec_top_ffpg_map.cheby --gen-hdl svec_top_ffpg_map.vhd
-- Generated on Fri Feb 24 09:30:58 2023 by tlevens
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity svec_top_ffpg_map is
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
-- a ROM containing the carrier metadata
metadata_i : in t_wishbone_master_in;
metadata_o : out t_wishbone_master_out;
-- FFPG core 0
ffpg0_i : in t_wishbone_master_in;
ffpg0_o : out t_wishbone_master_out;
-- FFPG core 1
ffpg1_i : in t_wishbone_master_in;
ffpg1_o : out t_wishbone_master_out
);
end svec_top_ffpg_map;
architecture syn of svec_top_ffpg_map is
signal adr_int : std_logic_vector(18 downto 2);
signal rd_req_int : std_logic;
signal wr_req_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal wb_en : std_logic;
signal ack_int : std_logic;
signal wb_rip : std_logic;
signal wb_wip : std_logic;
signal metadata_re : std_logic;
signal metadata_we : std_logic;
signal metadata_wt : std_logic;
signal metadata_rt : std_logic;
signal metadata_tr : std_logic;
signal metadata_wack : std_logic;
signal metadata_rack : std_logic;
signal ffpg0_re : std_logic;
signal ffpg0_we : std_logic;
signal ffpg0_wt : std_logic;
signal ffpg0_rt : std_logic;
signal ffpg0_tr : std_logic;
signal ffpg0_wack : std_logic;
signal ffpg0_rack : std_logic;
signal ffpg1_re : std_logic;
signal ffpg1_we : std_logic;
signal ffpg1_wt : std_logic;
signal ffpg1_rt : std_logic;
signal ffpg1_tr : std_logic;
signal ffpg1_wack : std_logic;
signal ffpg1_rack : std_logic;
signal rd_ack_d0 : std_logic;
signal rd_dat_d0 : std_logic_vector(31 downto 0);
signal wr_req_d0 : std_logic;
signal wr_adr_d0 : std_logic_vector(18 downto 2);
signal wr_dat_d0 : std_logic_vector(31 downto 0);
signal wr_sel_d0 : std_logic_vector(3 downto 0);
begin
-- WB decode signals
adr_int <= wb_i.adr(18 downto 2);
wb_en <= wb_i.cyc and wb_i.stb;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_rip <= '0';
else
wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
end if;
end if;
end process;
rd_req_int <= (wb_en and not wb_i.we) and not wb_rip;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_wip <= '0';
else
wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
end if;
end if;
end process;
wr_req_int <= (wb_en and wb_i.we) and not wb_wip;
ack_int <= rd_ack_int or wr_ack_int;
wb_o.ack <= ack_int;
wb_o.stall <= not ack_int and wb_en;
wb_o.rty <= '0';
wb_o.err <= '0';
-- pipelining for wr-in+rd-out
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wr_req_d0 <= '0';
else
rd_ack_int <= rd_ack_d0;
wb_o.dat <= rd_dat_d0;
wr_req_d0 <= wr_req_int;
wr_adr_d0 <= adr_int;
wr_dat_d0 <= wb_i.dat;
wr_sel_d0 <= wb_i.sel;
end if;
end if;
end process;
-- Interface metadata
metadata_tr <= metadata_wt or metadata_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
metadata_rt <= '0';
metadata_wt <= '0';
else
metadata_rt <= (metadata_rt or metadata_re) and not metadata_rack;
metadata_wt <= (metadata_wt or metadata_we) and not metadata_wack;
end if;
end if;
end process;
metadata_o.cyc <= metadata_tr;
metadata_o.stb <= metadata_tr;
metadata_wack <= metadata_i.ack and metadata_wt;
metadata_rack <= metadata_i.ack and metadata_rt;
metadata_o.adr <= ((25 downto 0 => '0') & adr_int(5 downto 2)) & (1 downto 0 => '0');
metadata_o.sel <= wr_sel_d0;
metadata_o.we <= metadata_wt;
metadata_o.dat <= wr_dat_d0;
-- Interface ffpg0
ffpg0_tr <= ffpg0_wt or ffpg0_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
ffpg0_rt <= '0';
ffpg0_wt <= '0';
else
ffpg0_rt <= (ffpg0_rt or ffpg0_re) and not ffpg0_rack;
ffpg0_wt <= (ffpg0_wt or ffpg0_we) and not ffpg0_wack;
end if;
end if;
end process;
ffpg0_o.cyc <= ffpg0_tr;
ffpg0_o.stb <= ffpg0_tr;
ffpg0_wack <= ffpg0_i.ack and ffpg0_wt;
ffpg0_rack <= ffpg0_i.ack and ffpg0_rt;
ffpg0_o.adr <= ((14 downto 0 => '0') & adr_int(16 downto 2)) & (1 downto 0 => '0');
ffpg0_o.sel <= wr_sel_d0;
ffpg0_o.we <= ffpg0_wt;
ffpg0_o.dat <= wr_dat_d0;
-- Interface ffpg1
ffpg1_tr <= ffpg1_wt or ffpg1_rt;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
ffpg1_rt <= '0';
ffpg1_wt <= '0';
else
ffpg1_rt <= (ffpg1_rt or ffpg1_re) and not ffpg1_rack;
ffpg1_wt <= (ffpg1_wt or ffpg1_we) and not ffpg1_wack;
end if;
end if;
end process;
ffpg1_o.cyc <= ffpg1_tr;
ffpg1_o.stb <= ffpg1_tr;
ffpg1_wack <= ffpg1_i.ack and ffpg1_wt;
ffpg1_rack <= ffpg1_i.ack and ffpg1_rt;
ffpg1_o.adr <= ((14 downto 0 => '0') & adr_int(16 downto 2)) & (1 downto 0 => '0');
ffpg1_o.sel <= wr_sel_d0;
ffpg1_o.we <= ffpg1_wt;
ffpg1_o.dat <= wr_dat_d0;
-- Process for write requests.
process (wr_adr_d0, wr_req_d0, metadata_wack, ffpg0_wack, ffpg1_wack) begin
metadata_we <= '0';
ffpg0_we <= '0';
ffpg1_we <= '0';
case wr_adr_d0(18 downto 17) is
when "00" =>
-- Submap metadata
metadata_we <= wr_req_d0;
wr_ack_int <= metadata_wack;
when "01" =>
-- Submap ffpg0
ffpg0_we <= wr_req_d0;
wr_ack_int <= ffpg0_wack;
when "11" =>
-- Submap ffpg1
ffpg1_we <= wr_req_d0;
wr_ack_int <= ffpg1_wack;
when others =>
wr_ack_int <= wr_req_d0;
end case;
end process;
-- Process for read requests.
process (adr_int, rd_req_int, metadata_i.dat, metadata_rack, ffpg0_i.dat,
ffpg0_rack, ffpg1_i.dat, ffpg1_rack) begin
-- By default ack read requests
rd_dat_d0 <= (others => 'X');
metadata_re <= '0';
ffpg0_re <= '0';
ffpg1_re <= '0';
case adr_int(18 downto 17) is
when "00" =>
-- Submap metadata
metadata_re <= rd_req_int;
rd_dat_d0 <= metadata_i.dat;
rd_ack_d0 <= metadata_rack;
when "01" =>
-- Submap ffpg0
ffpg0_re <= rd_req_int;
rd_dat_d0 <= ffpg0_i.dat;
rd_ack_d0 <= ffpg0_rack;
when "11" =>
-- Submap ffpg1
ffpg1_re <= rd_req_int;
rd_dat_d0 <= ffpg1_i.dat;
rd_ack_d0 <= ffpg1_rack;
when others =>
rd_ack_d0 <= rd_req_int;
end case;
end process;
end syn;
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