- 28 Feb, 2023 2 commits
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Tom Levens authored
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Tom Levens authored
- Front-panel "link" and "act" LEDs are not included in the base design constraints unless WR is enabled. - Constraints for the "aux" LEDs are missing, see: https://gitlab.cern.ch/be-cem-edl/fec/hardware-modules/spec/-/issues/15 Also switch to the "link" (green) LED for bus activity.
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- 27 Feb, 2023 2 commits
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Tom Levens authored
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Tom Levens authored
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- 26 Feb, 2023 2 commits
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Tom Levens authored
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Tom Levens authored
The SVEC base design has constraints for gc_sync_register but this is never instantiated in this design. Therefore ISE gives an error during synthesis. To avoid this error I have added an extra "dummy" gc_sync_register for synchronising the FP GPIO inputs. This can be removed once this issue is resolved: https://gitlab.cern.ch/be-cem-edl/fec/hardware-modules/svec/-/issues/25
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- 24 Feb, 2023 6 commits
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Tom Levens authored
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Tom Levens authored
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Tom Levens authored
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Tom Levens authored
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Tom Levens authored
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- 23 Feb, 2023 3 commits
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Tom Levens authored
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Tom Levens authored
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Tom Levens authored
Ensure transition to stop state only happens at end of sequence and that start only happens when stopped.
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- 20 Feb, 2023 1 commit
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Tom Levens authored
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- 19 Feb, 2023 3 commits
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Tom Levens authored
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Tom Levens authored
- Convert tabs to spaces - Convert DOS line endings to Unix - Clean whitespace at end of lines
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Tom Levens authored
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- 14 Sep, 2017 1 commit
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Jan Pospisil authored
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- 02 May, 2017 2 commits
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Jan Pospisil authored
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Jan Pospisil authored
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- 10 Apr, 2017 6 commits
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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- 06 Apr, 2017 4 commits
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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- 04 Apr, 2017 8 commits
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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