- 26 Sep, 2019 1 commit
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Dimitris Lampridis authored
[hdl] manually drive cheby-generated WB read data to 'X' for non-defined addresses. This helps with meeting timing because of smaller and simpler multiplexer logic.
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- 04 Sep, 2019 1 commit
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Dimitris Lampridis authored
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- 05 Aug, 2019 3 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 02 Aug, 2019 1 commit
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Dimitris Lampridis authored
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- 31 Jul, 2019 3 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 25 Jul, 2019 1 commit
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Dimitris Lampridis authored
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- 21 Jun, 2019 1 commit
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Dimitris Lampridis authored
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- 23 May, 2019 1 commit
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Dimitris Lampridis authored
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- 21 May, 2019 1 commit
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Dimitris Lampridis authored
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- 20 May, 2019 7 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
Re-aligment was performed using the WR-enabled FMC-ADC and the PPS signal coming out from the WR switch as signal input on channel #1, as well as external trigger input. The PPS signal was delivered to the FMC-ADC by means of a 40ns coaxial cable. External, internal and time triggering well all tested and calibrated using the above setup.
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
The new scheme (2x BUFIO2) is causing some routing troubles on the SVEC when WR is also present, so we provide a generic that allows to use the previous clocking scheme as well.
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- 06 May, 2019 2 commits
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Dimitris Lampridis authored
This is done in order to: a) Stop using an extra PLL for the ADC serdes and follow the clocking scheme proposed in UG382, v1.10, page 32, Figure 1-15. b) Decouple the LTC2174-specific code, as a first step to a more generalized acquisition core. c) Not distribute coregen-generated sources.
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Dimitris Lampridis authored
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- 03 May, 2019 1 commit
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Dimitris Lampridis authored
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- 02 May, 2019 2 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 30 Apr, 2019 1 commit
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Dimitris Lampridis authored
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- 21 Mar, 2019 1 commit
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Dimitris Lampridis authored
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- 01 Feb, 2019 1 commit
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Dimitris Lampridis authored
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- 17 Jan, 2019 12 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Tristan Gingold authored
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Tristan Gingold authored
Also generate the doc.
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Tristan Gingold authored
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Tristan Gingold authored
Also remove timetag_core component.
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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