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FMC ADC 100M 14b 4cha - Gateware
Commit c220d570 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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make trigger delay and tag adjustment calibration values configurable

parent 60e93911
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Showing with 45 additions and 16 deletions
hdl/rtl/fmc_adc_100Ms_core.vhd
View file @ c220d570
......@@ -44,6 +44,11 @@ entity fmc_adc_100Ms_core is
g_MULTISHOT_RAM_SIZE : natural := 2048;
-- Only used on Xilinx Spartan6 FPGAs
g_SPARTAN6_USE_PLL : boolean := TRUE;
-- External trigger delay calibration value
g_TRIG_DELAY_EXT : natural := 7;
-- Software and time trigger delay calibration value
g_TRIG_DELAY_SW : natural := 9;
-- WB interface configuration
g_WB_CSR_MODE : t_wishbone_interface_mode := PIPELINED;
g_WB_CSR_GRANULARITY : t_wishbone_address_granularity := BYTE);
port (
......@@ -197,7 +202,7 @@ architecture rtl of fmc_adc_100Ms_core is
signal ext_trig_delay_cnt : unsigned(31 downto 0);
signal ext_trig_delay_bsy : std_logic;
signal ext_trig_en : std_logic;
signal ext_trig_fixed_delay : std_logic_vector(9 downto 0);
signal ext_trig_fixed_delay : std_logic_vector(g_TRIG_DELAY_EXT+2 downto 0);
signal ext_trig_p, ext_trig_n : std_logic;
signal ext_trig_pol : std_logic;
signal int_trig : std_logic_vector(1 to 4);
......@@ -212,13 +217,13 @@ architecture rtl of fmc_adc_100Ms_core is
signal int_trig_thres_hyst : t_fmc_adc_vec16_array(1 to 4);
signal sw_trig : std_logic;
signal sw_trig_en : std_logic;
signal sw_trig_fixed_delay : std_logic_vector(11 downto 0);
signal sw_trig_fixed_delay : std_logic_vector(g_TRIG_DELAY_SW+2 downto 0);
signal time_trig : std_logic;
signal time_trig_en : std_logic;
signal time_trig_fixed_delay : std_logic_vector(11 downto 0);
signal time_trig_fixed_delay : std_logic_vector(g_TRIG_DELAY_SW+2 downto 0);
signal alt_time_trig : std_logic;
signal alt_time_trig_en : std_logic;
signal alt_time_trig_fixed_delay : std_logic_vector(11 downto 0);
signal alt_time_trig_fixed_delay : std_logic_vector(g_TRIG_DELAY_SW+2 downto 0);
signal trig : std_logic;
signal trig_align : std_logic_vector(8 downto 0);
signal trig_storage : std_logic_vector(31 downto 0);
......@@ -752,9 +757,9 @@ begin
-- We solve this by introducing individual delays to the other triggers. In doing
-- so, we always add more to account for the 3 clock cycles data delays mentioned
-- before. Thus:
-- * EXT triggers are delayed by 10 (7+3) cycles
-- * TIME triggers are delayed by 12 (9+3) cycles
-- * SOFT triggers are delayed by 12 (9+3) cycles
-- * EXT triggers are delayed by g_TRIG_DELAY_EXT + 3 cycles
-- * TIME triggers are delayed by g_TRIG_DELAY_SW + 3 cycles
-- * SOFT triggers are delayed by g_TRIG_DELAY_SW + 3 cycles
p_data_shift : process (fs_clk)
begin
......
hdl/rtl/fmc_adc_100Ms_core_pkg.vhd
View file @ c220d570
......@@ -53,6 +53,11 @@ package fmc_adc_100Ms_core_pkg is
g_MULTISHOT_RAM_SIZE : natural := 2048;
-- Only used on Xilinx Spartan6 FPGAs
g_SPARTAN6_USE_PLL : boolean := TRUE;
-- External trigger delay calibration value
g_TRIG_DELAY_EXT : natural := 7;
-- Software and time trigger delay calibration value
g_TRIG_DELAY_SW : natural := 9;
-- WB interface configuration
g_WB_CSR_MODE : t_wishbone_interface_mode := PIPELINED;
g_WB_CSR_GRANULARITY : t_wishbone_address_granularity := BYTE);
port (
......
hdl/rtl/fmc_adc_mezzanine.vhd
View file @ c220d570
......@@ -42,6 +42,15 @@ entity fmc_adc_mezzanine is
g_MULTISHOT_RAM_SIZE : natural := 2048;
-- Only used on Xilinx Spartan6 FPGAs
g_SPARTAN6_USE_PLL : boolean := TRUE;
-- External trigger delay calibration value
g_TRIG_DELAY_EXT : natural := 7;
-- Software and time trigger delay calibration value
g_TRIG_DELAY_SW : natural := 9;
-- Value to be subtracted from trigger tag coarse counter.
-- This is useful if you know that the system introduces
-- some systematic delay wrt the actual trigger time
g_TAG_ADJUST : natural := 24;
-- WB interface configuration
g_WB_MODE : t_wishbone_interface_mode := PIPELINED;
g_WB_GRANULARITY : t_wishbone_address_granularity := BYTE);
port (
......@@ -435,14 +444,16 @@ begin
-- Offset DACs control (CLR_N)
-- ADC core control and status
------------------------------------------------------------------------------
cmp_fmc_adc_100Ms_core : fmc_adc_100Ms_core
generic map (
g_WB_CSR_MODE => CLASSIC,
g_WB_CSR_GRANULARITY => BYTE,
g_MULTISHOT_RAM_SIZE => g_MULTISHOT_RAM_SIZE,
g_SPARTAN6_USE_PLL => g_SPARTAN6_USE_PLL,
g_MULTISHOT_RAM_SIZE => g_MULTISHOT_RAM_SIZE
)
port map(
g_TRIG_DELAY_EXT => g_TRIG_DELAY_EXT,
g_TRIG_DELAY_SW => g_TRIG_DELAY_SW,
g_WB_CSR_MODE => CLASSIC,
g_WB_CSR_GRANULARITY => BYTE)
port map (
sys_clk_i => sys_clk_i,
sys_rst_n_i => sys_rst_n_i,
......@@ -491,8 +502,7 @@ begin
gpio_ssr_ch2_o => gpio_ssr_ch2_o,
gpio_ssr_ch3_o => gpio_ssr_ch3_o,
gpio_ssr_ch4_o => gpio_ssr_ch4_o,
gpio_si570_oe_o => gpio_si570_oe_o
);
gpio_si570_oe_o => gpio_si570_oe_o);
------------------------------------------------------------------------------
-- Mezzanine 1-wire master
......@@ -584,7 +594,7 @@ begin
generic map (
-- Systematic delay introduced to the time tag by the FMC-ADC-100M core.
-- Measured experimentally.
g_TAG_ADJUST => 24)
g_TAG_ADJUST => g_TAG_ADJUST)
port map(
clk_i => sys_clk_i,
rst_n_i => sys_rst_n_i,
......
hdl/rtl/fmc_adc_mezzanine_pkg.vhd
View file @ c220d570
......@@ -44,9 +44,18 @@ package fmc_adc_mezzanine_pkg is
------------------------------------------------------------------------------
component fmc_adc_mezzanine
generic (
g_MULTISHOT_RAM_SIZE : natural := 2048;
g_MULTISHOT_RAM_SIZE : natural := 2048;
-- Only used on Xilinx Spartan6 FPGAs
g_SPARTAN6_USE_PLL : boolean := TRUE;
-- External trigger delay calibration value
g_TRIG_DELAY_EXT : natural := 7;
-- Software and time trigger delay calibration value
g_TRIG_DELAY_SW : natural := 9;
-- Value to be subtracted from trigger tag coarse counter.
-- This is useful if you know that the system introduces
-- some systematic delay wrt the actual trigger time
g_TAG_ADJUST : natural := 24;
-- WB interface configuration
g_WB_MODE : t_wishbone_interface_mode := PIPELINED;
g_WB_GRANULARITY : t_wishbone_address_granularity := BYTE);
port (
......
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