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FMC ADC 100M 14b 4cha - Gateware
Commit 89dde8f4 authored by Tristan Gingold's avatar Tristan Gingold Committed by Dimitris Lampridis
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alternate trigger: add a test, and fix.

parent 9fe7aae8
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Showing with 79 additions and 26 deletions
hdl/rtl/fmc_adc_alt_trigin.vhd
View file @ 89dde8f4
......@@ -18,10 +18,10 @@ entity alt_trigin is
ctrl_wr_o : out std_logic;
-- Time (seconds) to trigger
seconds_i : in std_logic_vector(63 downto 0);
seconds_o : out std_logic_vector(63 downto 0);
-- Time (cycles) to trigger
cycles_i : in std_logic_vector(31 downto 0)
cycles_o : out std_logic_vector(31 downto 0)
);
end alt_trigin;
......@@ -32,6 +32,8 @@ architecture syn of alt_trigin is
signal ack_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal seconds_reg : std_logic_vector(63 downto 0);
signal cycles_reg : std_logic_vector(31 downto 0);
signal wr_ack_done_int : std_logic;
signal reg_rdat_int : std_logic_vector(31 downto 0);
signal rd_ack1_int : std_logic;
......@@ -48,6 +50,8 @@ begin
wb_o.err <= '0';
-- Assign outputs
seconds_o <= seconds_reg;
cycles_o <= cycles_reg;
-- Process for write requests.
process (clk_i, rst_n_i) begin
......@@ -55,6 +59,9 @@ begin
wr_ack_int <= '0';
wr_ack_done_int <= '0';
ctrl_wr_o <= '0';
seconds_reg <= "0000000000000000000000000000000000000000000000000000000000000000";
seconds_reg <= "0000000000000000000000000000000000000000000000000000000000000000";
cycles_reg <= "00000000000000000000000000000000";
elsif rising_edge(clk_i) then
ctrl_wr_o <= '0';
if wr_int = '1' then
......@@ -66,7 +73,7 @@ begin
when "0" =>
-- Register ctrl
ctrl_wr_o <= '1';
ctrl_enable_o <= wb_i.dat(1);
ctrl_enable_o <= wb_i.dat(0);
wr_ack_int <= not wr_ack_done_int;
when others =>
wr_ack_int <= not wr_ack_done_int;
......@@ -75,9 +82,11 @@ begin
case wb_i.adr(2 downto 2) is
when "0" =>
-- Register seconds
seconds_reg(63 downto 32) <= wb_i.dat;
wr_ack_int <= not wr_ack_done_int;
when "1" =>
-- Register seconds
seconds_reg(31 downto 0) <= wb_i.dat;
wr_ack_int <= not wr_ack_done_int;
when others =>
wr_ack_int <= not wr_ack_done_int;
......@@ -86,6 +95,7 @@ begin
case wb_i.adr(2 downto 2) is
when "0" =>
-- Register cycles
cycles_reg <= wb_i.dat;
wr_ack_int <= not wr_ack_done_int;
when others =>
wr_ack_int <= not wr_ack_done_int;
......@@ -107,28 +117,30 @@ begin
elsif rising_edge(clk_i) then
if rd_int = '1' and rd_ack1_int = '0' then
rd_ack1_int <= '1';
reg_rdat_int <= (others => '0');
case wb_i.adr(4 downto 3) is
when "00" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- ctrl
reg_rdat_int(0) <= ctrl_enable_i;
when others =>
end case;
when "01" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- seconds
reg_rdat_int <= seconds_i(63 downto 32);
reg_rdat_int <= seconds_reg(63 downto 32);
when "1" =>
-- seconds
reg_rdat_int <= seconds_i(31 downto 0);
reg_rdat_int <= seconds_reg(31 downto 0);
when others =>
end case;
when "10" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- cycles
reg_rdat_int <= cycles_i;
reg_rdat_int <= cycles_reg;
when others =>
end case;
when others =>
......
hdl/rtl/fmc_adc_mezzanine.vhd
View file @ 89dde8f4
......@@ -617,14 +617,12 @@ begin
ctrl_enable_o => alt_trigin_enable_out,
ctrl_wr_o => alt_trigin_enable_wr,
seconds_i => alt_trigin_secs,
cycles_i => alt_trigin_cycs
seconds_o => alt_trigin_secs,
cycles_o => alt_trigin_cycs
);
alt_trigin_secs(39 downto 0) <= alt_trigin_tag.seconds;
alt_trigin_secs(63 downto 40) <= (others => '0');
alt_trigin_cycs(27 downto 0) <= alt_trigin_tag.coarse;
alt_trigin_cycs(31 downto 28) <= (others => '0');
alt_trigin_tag <= (seconds => alt_trigin_secs(39 downto 0),
coarse => alt_trigin_cycs(27 downto 0));
-- Unused wishbone signals
cnx_slave_out(c_WB_SLAVE_TIMETAG).err <= '0';
......
hdl/rtl/wb_gen/Makefile
View file @ 89dde8f4
......@@ -15,8 +15,7 @@ fmc_adc_eic:
$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
fmc_adc_alt_trigin:
$(CHEBY) --gen-hdl=$(RTL)/$@.vhd -i $@.cheby
$(CHEBY) --gen-hdl=$(RTL)/$@.vhd --gen-consts=$(SIM)/$@.v -i $@.cheby
fmc_adc_alt_trigout:
$(CHEBY) --gen-hdl=$(RTL)/$@.vhd -i $@.cheby
hdl/rtl/wb_gen/fmc_adc_alt_trigin.cheby
View file @ 89dde8f4
......@@ -13,7 +13,7 @@ memory-map:
- field:
name: enable
description: Enable trigger, cleared when triggered
range: 1
range: 0
x-hdl:
type: wire
x-hdl:
......@@ -23,10 +23,10 @@ memory-map:
description: Time (seconds) to trigger
width: 64
type: unsigned
access: ro
access: rw
- reg:
name: cycles
description: Time (cycles) to trigger
width: 32
type: unsigned
access: ro
access: rw
hdl/testbench/fmc_adc_mezzanine/main.sv
View file @ 89dde8f4
......@@ -3,6 +3,7 @@
`include "vhd_wishbone_master.svh"
`include "fmc_adc_100Ms_csr.v"
`include "timetag_core_regs.v"
`include "fmc_adc_alt_trigin.v"
`define SDB_ADDR 'h0000
`define CSR_BASE 'h1000
......@@ -161,7 +162,7 @@ module main;
initial begin
CWishboneAccessor acc;
CWishboneAccessor acc, trigin_acc;
uint64_t val, expected;
$timeformat (-6, 3, "us", 10);
......@@ -169,7 +170,7 @@ module main;
acc = Host.get_accessor();
acc.set_mode(PIPELINED);
acc.set_mode(PIPELINED);
trigin_acc = Trigin.get_accessor();
#1us;
......@@ -208,6 +209,7 @@ module main;
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_TRIG_THRES, val);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_TRIG_THRES, val);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_TRIG_THRES, val);
// Enable only software trigger.
val = (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_SW_OFFSET);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
......@@ -226,7 +228,7 @@ module main;
acc.write(`TAG_BASE + `ADDR_TIMETAG_CORE_COARSE, 'h00000000); // timetag core ticks
wait (acq_fsm_state == 1);
$display("<%t> START ACQ 1/4", $realtime);
$display("<%t> START ACQ 1", $realtime);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CTL, 'h00000001); // FSM start
#200ns;
......@@ -234,13 +236,13 @@ module main;
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SW_TRIG, 'hFFFFFFFF); // soft trigger
wait (acq_fsm_state == 1);
$display("<%t> END ACQ 1/4", $realtime);
$display("<%t> END ACQ 1", $realtime);
#200ns;
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h00000003); // #nshots: 3x multi-shot acq
$display("<%t> START ACQ 2/4", $realtime);
$display("<%t> START ACQ 2", $realtime);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CTL, 'h00000001); // FSM start
#500ns;
......@@ -256,7 +258,7 @@ module main;
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SW_TRIG, 'hFFFFFFFC); // soft trigger
wait (acq_fsm_state == 1);
$display("<%t> END ACQ 2/4", $realtime);
$display("<%t> END ACQ 2", $realtime);
#1us;
......@@ -268,7 +270,7 @@ module main;
(1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_CH3_OFFSET);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
$display("<%t> START ACQ 3/4", $realtime);
$display("<%t> START ACQ 3", $realtime);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CTL, 'h00000001); // FSM start
#1us;
......@@ -304,7 +306,7 @@ module main;
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h0000002);
$display("<%t> START ACQ 4/4", $realtime);
$display("<%t> START ACQ 4", $realtime);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CTL, 'h00000001); // FSM start
#1us;
......@@ -322,7 +324,49 @@ module main;
ext_trig <= 1'b0;
wait (acq_fsm_state == 1);
$display("<%t> END ACQ 4/4", $realtime);
$display("<%t> END ACQ 4", $realtime);
#1us;
// set time trigger
trigin_acc.write(`ADDR_ALT_TRIGIN_SECONDS + 0, 'h00000032);
trigin_acc.write(`ADDR_ALT_TRIGIN_SECONDS + 4, 'h00005a34);
trigin_acc.write(`ADDR_ALT_TRIGIN_CYCLES + 0, 'h00001000);
trigin_acc.write(`ADDR_ALT_TRIGIN_CTRL, `ALT_TRIGIN_CTRL_ENABLE);
trigin_acc.read(`ADDR_ALT_TRIGIN_CTRL, val);
expected = `ALT_TRIGIN_CTRL_ENABLE;
if (val != expected)
begin
$fatal (1, "trigin ctrl error (got 0x%8x, expected 0x%8x).",
val, expected);
end
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES, 'h00000001);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES, 'h00000008);
// FMC-ADC core trigger configuration
val = (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_ALT_TIME_OFFSET);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h0000001);
$display("<%t> START ACQ 5", $realtime);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CTL, 'h00000001); // FSM start
#1us;
wait (acq_fsm_state == 1);
trigin_acc.read(`ADDR_ALT_TRIGIN_CTRL, val);
expected = 0;
if (val != expected)
begin
$fatal (1, "trigin ctrl error (got 0x%8x, expected 0x%8x).",
val, expected);
end
$display("<%t> END ACQ 5", $realtime);
#1us;
......
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