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FMC ADC 100M 14b 4cha - Gateware
Commit 3911c3bf authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: revert to WB classic and use the updated xwb_register module

parent 0bf73130
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Showing with 9 additions and 13 deletions
general-cores @ d26be4fe
Subproject commit 4e0bee168f44cde5db5bc8ff2fd8a94456ba8786
Subproject commit d26be4fea0a0f38c0c095413c316a463462be23d
hdl/rtl/fmc_adc_100Ms_core.vhd
View file @ 3911c3bf
......@@ -393,7 +393,7 @@ begin
cmp_csr_wb_slave_adapter : wb_slave_adapter
generic map (
g_master_use_struct => TRUE,
g_master_mode => PIPELINED,
g_master_mode => CLASSIC,
g_master_granularity => WORD,
g_slave_use_struct => TRUE,
g_slave_mode => g_WB_CSR_MODE,
......
hdl/rtl/fmc_adc_mezzanine.vhd
View file @ 3911c3bf
......@@ -280,7 +280,7 @@ begin
cmp_fmc_wb_slave_adapter_in : wb_slave_adapter
generic map (
g_master_use_struct => TRUE,
g_master_mode => PIPELINED,
g_master_mode => CLASSIC,
g_master_granularity => BYTE,
g_slave_use_struct => TRUE,
g_slave_mode => g_WB_MODE,
......@@ -296,10 +296,7 @@ begin
-- Additional register to help timing
cmp_xwb_register : xwb_register
generic map (
g_WB_MODE => PIPELINED,
-- Do not register the return path (ACK/STALL).
-- See xwb_register for more details.
g_FULL_REG => FALSE)
g_WB_MODE => CLASSIC)
port map (
rst_n_i => sys_rst_n_i,
clk_i => sys_clk_i,
......@@ -331,7 +328,7 @@ begin
------------------------------------------------------------------------------
cmp_fmc_sys_i2c : xwb_i2c_master
generic map(
g_interface_mode => PIPELINED,
g_interface_mode => CLASSIC,
g_address_granularity => BYTE
)
port map (
......@@ -364,7 +361,7 @@ begin
------------------------------------------------------------------------------
cmp_fmc_spi : xwb_spi
generic map(
g_interface_mode => PIPELINED,
g_interface_mode => CLASSIC,
g_address_granularity => BYTE
)
port map (
......@@ -408,7 +405,7 @@ begin
------------------------------------------------------------------------------
cmp_fmc_i2c : xwb_i2c_master
generic map(
g_interface_mode => PIPELINED,
g_interface_mode => CLASSIC,
g_address_granularity => BYTE
)
port map (
......@@ -443,7 +440,7 @@ begin
------------------------------------------------------------------------------
cmp_fmc_adc_100Ms_core : fmc_adc_100Ms_core
generic map (
g_WB_CSR_MODE => PIPELINED,
g_WB_CSR_MODE => CLASSIC,
g_WB_CSR_GRANULARITY => BYTE,
g_MULTISHOT_RAM_SIZE => g_MULTISHOT_RAM_SIZE
)
......@@ -507,7 +504,7 @@ begin
------------------------------------------------------------------------------
cmp_fmc_onewire : xwb_onewire_master
generic map(
g_interface_mode => PIPELINED,
g_interface_mode => CLASSIC,
g_address_granularity => BYTE,
g_num_ports => 1,
g_ow_btp_normal => "5.0",
......
hdl/top/svec_ref_design/svec_ref_fmc_adc_100Ms.vhd
View file @ 3911c3bf
......@@ -492,7 +492,6 @@ begin
-- reset for mezzanines
-- including soft reset, with re-sync from 62.5MHz domain
-- and registers to help with timing
cmp_fmc_sw_reset_sync : gc_sync_ffs
port map (
clk_i => clk_ref_125m,
......
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