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FMC ADC 100M 14b 4cha - Gateware
Commit afdb9516 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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move trigger forwarding control to main CSR

parent a60eac03
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Showing with 321 additions and 274 deletions
doc/manual/fmc_adc_100Ms_csr.tex
View file @ afdb9516
......@@ -354,6 +354,31 @@ Channel 3 internal threshold trigger
@code{CH4}
@tab @code{0} @tab
Channel 4 internal threshold trigger
@item @code{16}
@tab R/W @tab
@code{FWD_EXT}
@tab @code{0} @tab
Forward external trigger to trigger out
@item @code{24}
@tab R/W @tab
@code{FWD_CH1}
@tab @code{0} @tab
Forward channel 1 internal threshold trigger to trigger out
@item @code{25}
@tab R/W @tab
@code{FWD_CH2}
@tab @code{0} @tab
Forward channel 2 internal threshold trigger to trigger out
@item @code{26}
@tab R/W @tab
@code{FWD_CH3}
@tab @code{0} @tab
Forward channel 3 internal threshold trigger to trigger out
@item @code{27}
@tab R/W @tab
@code{FWD_CH4}
@tab @code{0} @tab
Forward channel 4 internal threshold trigger to trigger out
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
......@@ -365,6 +390,11 @@ Channel 4 internal threshold trigger
@item @code{ch2} @tab 0: disable@*1: enable
@item @code{ch3} @tab 0: disable@*1: enable
@item @code{ch4} @tab 0: disable@*1: enable
@item @code{fwd_ext} @tab 0: disable@*1: enable
@item @code{fwd_ch1} @tab 0: disable@*1: enable
@item @code{fwd_ch2} @tab 0: disable@*1: enable
@item @code{fwd_ch3} @tab 0: disable@*1: enable
@item @code{fwd_ch4} @tab 0: disable@*1: enable
@end multitable
@regsection @code{trig_pol} - Trigger polarity
@multitable @columnfractions .10 .10 .15 .10 .55
......
hdl/rtl/fmc_adc_100Ms_core.vhd
View file @ afdb9516
......@@ -741,6 +741,8 @@ begin
gpio_ssr_ch3_o <= csr_regout.ch3_ctl_ssr_o;
gpio_ssr_ch4_o <= csr_regout.ch4_ctl_ssr_o;
-- NOTE: trigger forwards are read from CSR in the b_trigout block later
gain_calibr <= csr_regout.ch4_gain_val_o & csr_regout.ch3_gain_val_o &
csr_regout.ch2_gain_val_o & csr_regout.ch1_gain_val_o;
......@@ -1766,11 +1768,6 @@ begin
wr_valid_i => wr_tm_time_valid_i,
ts_present_i => trigout_fifo_not_empty,
ch1_enable_o => trigout_en(0),
ch2_enable_o => trigout_en(1),
ch3_enable_o => trigout_en(2),
ch4_enable_o => trigout_en(3),
ext_enable_o => trigout_en(4),
ts_sec_i => trigout_fifo_dout(t_trigout_data_seconds'range),
ch1_mask_i => trigout_fifo_dout(t_trigout_data_channels'right + 0),
ch2_mask_i => trigout_fifo_dout(t_trigout_data_channels'right + 1),
......@@ -1802,6 +1799,12 @@ begin
ppulse_o => trigout_triggers(i));
end generate;
trigout_en(0) <= csr_regout.trig_en_fwd_ch1_o;
trigout_en(1) <= csr_regout.trig_en_fwd_ch2_o;
trigout_en(2) <= csr_regout.trig_en_fwd_ch3_o;
trigout_en(3) <= csr_regout.trig_en_fwd_ch4_o;
trigout_en(4) <= csr_regout.trig_en_fwd_ext_o;
trigout_trig <= f_reduce_or (trigout_triggers and trigout_en);
trigout_fifo_wr <= trigout_trig and not trigout_fifo_full;
......
hdl/rtl/fmc_adc_100Ms_csr.vhd
View file @ afdb9516
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../fmc_adc_100Ms_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created : Tue Nov 6 10:51:54 2018
-- Created : Thu Mar 21 13:57:25 2019
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -76,6 +76,11 @@ signal fmc_adc_100ms_csr_trig_en_ch3_sync1 : std_logic ;
signal fmc_adc_100ms_csr_trig_en_ch4_int : std_logic ;
signal fmc_adc_100ms_csr_trig_en_ch4_sync0 : std_logic ;
signal fmc_adc_100ms_csr_trig_en_ch4_sync1 : std_logic ;
signal fmc_adc_100ms_csr_trig_en_fwd_ext_int : std_logic ;
signal fmc_adc_100ms_csr_trig_en_fwd_ch1_int : std_logic ;
signal fmc_adc_100ms_csr_trig_en_fwd_ch2_int : std_logic ;
signal fmc_adc_100ms_csr_trig_en_fwd_ch3_int : std_logic ;
signal fmc_adc_100ms_csr_trig_en_fwd_ch4_int : std_logic ;
signal fmc_adc_100ms_csr_trig_pol_ext_int : std_logic ;
signal fmc_adc_100ms_csr_trig_pol_ext_sync0 : std_logic ;
signal fmc_adc_100ms_csr_trig_pol_ext_sync1 : std_logic ;
......@@ -248,6 +253,11 @@ begin
fmc_adc_100ms_csr_trig_en_ch2_int <= '0';
fmc_adc_100ms_csr_trig_en_ch3_int <= '0';
fmc_adc_100ms_csr_trig_en_ch4_int <= '0';
fmc_adc_100ms_csr_trig_en_fwd_ext_int <= '0';
fmc_adc_100ms_csr_trig_en_fwd_ch1_int <= '0';
fmc_adc_100ms_csr_trig_en_fwd_ch2_int <= '0';
fmc_adc_100ms_csr_trig_en_fwd_ch3_int <= '0';
fmc_adc_100ms_csr_trig_en_fwd_ch4_int <= '0';
fmc_adc_100ms_csr_trig_pol_ext_int <= '0';
fmc_adc_100ms_csr_trig_pol_ch1_int <= '0';
fmc_adc_100ms_csr_trig_pol_ch2_int <= '0';
......@@ -516,6 +526,11 @@ begin
fmc_adc_100ms_csr_trig_en_ch2_int <= wrdata_reg(9);
fmc_adc_100ms_csr_trig_en_ch3_int <= wrdata_reg(10);
fmc_adc_100ms_csr_trig_en_ch4_int <= wrdata_reg(11);
fmc_adc_100ms_csr_trig_en_fwd_ext_int <= wrdata_reg(16);
fmc_adc_100ms_csr_trig_en_fwd_ch1_int <= wrdata_reg(24);
fmc_adc_100ms_csr_trig_en_fwd_ch2_int <= wrdata_reg(25);
fmc_adc_100ms_csr_trig_en_fwd_ch3_int <= wrdata_reg(26);
fmc_adc_100ms_csr_trig_en_fwd_ch4_int <= wrdata_reg(27);
end if;
rddata_reg(0) <= fmc_adc_100ms_csr_trig_en_ext_int;
rddata_reg(1) <= fmc_adc_100ms_csr_trig_en_sw_int;
......@@ -525,6 +540,11 @@ begin
rddata_reg(9) <= fmc_adc_100ms_csr_trig_en_ch2_int;
rddata_reg(10) <= fmc_adc_100ms_csr_trig_en_ch3_int;
rddata_reg(11) <= fmc_adc_100ms_csr_trig_en_ch4_int;
rddata_reg(16) <= fmc_adc_100ms_csr_trig_en_fwd_ext_int;
rddata_reg(24) <= fmc_adc_100ms_csr_trig_en_fwd_ch1_int;
rddata_reg(25) <= fmc_adc_100ms_csr_trig_en_fwd_ch2_int;
rddata_reg(26) <= fmc_adc_100ms_csr_trig_en_fwd_ch3_int;
rddata_reg(27) <= fmc_adc_100ms_csr_trig_en_fwd_ch4_int;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(6) <= 'X';
......@@ -533,7 +553,6 @@ begin
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
......@@ -541,10 +560,6 @@ begin
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
......@@ -1522,6 +1537,16 @@ begin
end process;
-- Forward external trigger to trigger out
regs_o.trig_en_fwd_ext_o <= fmc_adc_100ms_csr_trig_en_fwd_ext_int;
-- Forward channel 1 internal threshold trigger to trigger out
regs_o.trig_en_fwd_ch1_o <= fmc_adc_100ms_csr_trig_en_fwd_ch1_int;
-- Forward channel 2 internal threshold trigger to trigger out
regs_o.trig_en_fwd_ch2_o <= fmc_adc_100ms_csr_trig_en_fwd_ch2_int;
-- Forward channel 3 internal threshold trigger to trigger out
regs_o.trig_en_fwd_ch3_o <= fmc_adc_100ms_csr_trig_en_fwd_ch3_int;
-- Forward channel 4 internal threshold trigger to trigger out
regs_o.trig_en_fwd_ch4_o <= fmc_adc_100ms_csr_trig_en_fwd_ch4_int;
-- External trigger input
-- synchronizer chain for field : External trigger input (type RW/RO, clk_sys_i <-> fs_clk_i)
process (fs_clk_i, rst_n_i)
......
hdl/rtl/fmc_adc_100Ms_csr_wbgen2_pkg.vhd
View file @ afdb9516
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../fmc_adc_100Ms_csr_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created : Tue Nov 6 10:51:54 2018
-- Created : Thu Mar 21 13:57:25 2019
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -85,6 +85,11 @@ package fmc_adc_100ms_csr_wbgen2_pkg is
trig_en_ch2_o : std_logic;
trig_en_ch3_o : std_logic;
trig_en_ch4_o : std_logic;
trig_en_fwd_ext_o : std_logic;
trig_en_fwd_ch1_o : std_logic;
trig_en_fwd_ch2_o : std_logic;
trig_en_fwd_ch3_o : std_logic;
trig_en_fwd_ch4_o : std_logic;
trig_pol_ext_o : std_logic;
trig_pol_ch1_o : std_logic;
trig_pol_ch2_o : std_logic;
......@@ -145,6 +150,11 @@ package fmc_adc_100ms_csr_wbgen2_pkg is
trig_en_ch2_o => '0',
trig_en_ch3_o => '0',
trig_en_ch4_o => '0',
trig_en_fwd_ext_o => '0',
trig_en_fwd_ch1_o => '0',
trig_en_fwd_ch2_o => '0',
trig_en_fwd_ch3_o => '0',
trig_en_fwd_ch4_o => '0',
trig_pol_ext_o => '0',
trig_pol_ch1_o => '0',
trig_pol_ch2_o => '0',
......
hdl/rtl/fmc_adc_alt_trigout.vhd
View file @ afdb9516
......@@ -22,21 +22,6 @@ entity alt_trigout is
-- Set when the timestamp fifo is not empty
ts_present_i : in std_logic;
-- Enable channel 1 trigger
ch1_enable_o : out std_logic;
-- Enable channel 2 trigger
ch2_enable_o : out std_logic;
-- Enable channel 3 trigger
ch3_enable_o : out std_logic;
-- Enable channel 4 trigger
ch4_enable_o : out std_logic;
-- Enable external trigger
ext_enable_o : out std_logic;
-- Seconds part of the timestamp
ts_sec_i : in std_logic_vector(39 downto 0);
......@@ -68,11 +53,6 @@ architecture syn of alt_trigout is
signal ack_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal ch1_enable_reg : std_logic;
signal ch2_enable_reg : std_logic;
signal ch3_enable_reg : std_logic;
signal ch4_enable_reg : std_logic;
signal ext_enable_reg : std_logic;
signal wr_ack_done_int : std_logic;
signal reg_rdat_int : std_logic_vector(31 downto 0);
signal rd_ack1_int : std_logic;
......@@ -89,22 +69,12 @@ begin
wb_o.err <= '0';
-- Assign outputs
ch1_enable_o <= ch1_enable_reg;
ch2_enable_o <= ch2_enable_reg;
ch3_enable_o <= ch3_enable_reg;
ch4_enable_o <= ch4_enable_reg;
ext_enable_o <= ext_enable_reg;
-- Process for write requests.
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
wr_ack_int <= '0';
wr_ack_done_int <= '0';
ch1_enable_reg <= '0';
ch2_enable_reg <= '0';
ch3_enable_reg <= '0';
ch4_enable_reg <= '0';
ext_enable_reg <= '0';
elsif rising_edge(clk_i) then
if wr_int = '1' then
-- Write in progress
......@@ -115,15 +85,8 @@ begin
when "0" =>
-- Register status
wr_ack_int <= not wr_ack_done_int;
when "1" =>
-- Register enable
ch1_enable_reg <= wb_i.dat(0);
ch2_enable_reg <= wb_i.dat(1);
ch3_enable_reg <= wb_i.dat(2);
ch4_enable_reg <= wb_i.dat(3);
ext_enable_reg <= wb_i.dat(8);
wr_ack_int <= not wr_ack_done_int;
when others =>
wr_ack_int <= not wr_ack_done_int;
end case;
when "01" =>
case wb_i.adr(2 downto 2) is
......@@ -173,13 +136,6 @@ begin
reg_rdat_int(1) <= wr_link_i;
reg_rdat_int(2) <= wr_valid_i;
reg_rdat_int(8) <= ts_present_i;
when "1" =>
-- enable
reg_rdat_int(0) <= ch1_enable_reg;
reg_rdat_int(1) <= ch2_enable_reg;
reg_rdat_int(2) <= ch3_enable_reg;
reg_rdat_int(3) <= ch4_enable_reg;
reg_rdat_int(8) <= ext_enable_reg;
when others =>
end case;
when "01" =>
......@@ -225,10 +181,6 @@ begin
-- status
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "1" =>
-- enable
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when others =>
end case;
when "01" =>
......
hdl/rtl/fmc_adc_mezzanine_pkg.vhd
View file @ afdb9516
......@@ -69,6 +69,14 @@ package fmc_adc_mezzanine_pkg is
eic_irq_o : out std_logic;
acq_cfg_ok_o : out std_logic;
-- Alternate trigger input wishbone interface
wb_trigin_slave_i : in t_wishbone_slave_in := c_DUMMY_WB_SLAVE_IN;
wb_trigin_slave_o : out t_wishbone_slave_out;
-- Trigout wishbone interface
wb_trigout_slave_i : in t_wishbone_slave_in := c_DUMMY_WB_SLAVE_IN;
wb_trigout_slave_o : out t_wishbone_slave_out;
-- FMC interface
ext_trigger_p_i : in std_logic; -- External trigger
ext_trigger_n_i : in std_logic;
......
hdl/rtl/wb_gen/Makefile
View file @ afdb9516
......@@ -4,7 +4,7 @@ RTL=../
SIM=../../testbench/include/
TEX=../../../doc/manual/
all: fmc_adc_100Ms_csr fmc_adc_eic
all: fmc_adc_100Ms_csr fmc_adc_eic fmc_adc_alt_trigin fmc_adc_alt_trigout
fmc_adc_100Ms_csr:
$(WBGEN2) -l vhdl -H record -V $(RTL)$@.vhd -p $(RTL)$@_wbgen2_pkg.vhd -f html -D $@.htm -C $@.h -K $(SIM)$@.v $@.wb
......
hdl/rtl/wb_gen/fmc_adc_100Ms_csr.h
View file @ afdb9516
......@@ -3,7 +3,7 @@
* File : fmc_adc_100Ms_csr.h
* Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
* Created : Tue Nov 6 10:51:54 2018
* Created : Thu Mar 21 13:57:25 2019
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -130,6 +130,21 @@
/* definitions for field: Channel 4 internal threshold trigger in reg: Trigger enable */
#define FMC_ADC_100MS_CSR_TRIG_EN_CH4 WBGEN2_GEN_MASK(11, 1)
/* definitions for field: Forward external trigger to trigger out in reg: Trigger enable */
#define FMC_ADC_100MS_CSR_TRIG_EN_FWD_EXT WBGEN2_GEN_MASK(16, 1)
/* definitions for field: Forward channel 1 internal threshold trigger to trigger out in reg: Trigger enable */
#define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH1 WBGEN2_GEN_MASK(24, 1)
/* definitions for field: Forward channel 2 internal threshold trigger to trigger out in reg: Trigger enable */
#define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH2 WBGEN2_GEN_MASK(25, 1)
/* definitions for field: Forward channel 3 internal threshold trigger to trigger out in reg: Trigger enable */
#define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH3 WBGEN2_GEN_MASK(26, 1)
/* definitions for field: Forward channel 4 internal threshold trigger to trigger out in reg: Trigger enable */
#define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH4 WBGEN2_GEN_MASK(27, 1)
/* definitions for register: Trigger polarity */
/* definitions for field: External trigger input in reg: Trigger polarity */
......
hdl/rtl/wb_gen/fmc_adc_100Ms_csr.htm
View file @ afdb9516
......@@ -1450,6 +1450,91 @@ fmc_adc_100ms_csr_trig_en_ch4_o
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_100ms_csr_trig_en_fwd_ext_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_100ms_csr_trig_en_fwd_ch1_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_100ms_csr_trig_en_fwd_ch2_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_100ms_csr_trig_en_fwd_ch3_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_100ms_csr_trig_en_fwd_ch4_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
......@@ -4554,17 +4639,17 @@ TRIG_EN
<td class="td_unused">
-
</td>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=1 class="td_field">
FWD_CH4
</td>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=1 class="td_field">
FWD_CH3
</td>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=1 class="td_field">
FWD_CH2
</td>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=1 class="td_field">
FWD_CH1
</td>
</tr>
</table>
......@@ -4617,8 +4702,8 @@ TRIG_EN
<td class="td_unused">
-
</td>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=1 class="td_field">
FWD_EXT
</td>
</tr>
</table>
......@@ -4763,6 +4848,26 @@ CH3
CH4
</b>[<i>read/write</i>]: Channel 4 internal threshold trigger
<br>0: disable<br>1: enable
<li><b>
FWD_EXT
</b>[<i>read/write</i>]: Forward external trigger to trigger out
<br>0: disable<br>1: enable
<li><b>
FWD_CH1
</b>[<i>read/write</i>]: Forward channel 1 internal threshold trigger to trigger out
<br>0: disable<br>1: enable
<li><b>
FWD_CH2
</b>[<i>read/write</i>]: Forward channel 2 internal threshold trigger to trigger out
<br>0: disable<br>1: enable
<li><b>
FWD_CH3
</b>[<i>read/write</i>]: Forward channel 3 internal threshold trigger to trigger out
<br>0: disable<br>1: enable
<li><b>
FWD_CH4
</b>[<i>read/write</i>]: Forward channel 4 internal threshold trigger to trigger out
<br>0: disable<br>1: enable
</ul>
<a name="TRIG_POL"></a>
<h3><a name="sect_3_5">3.5. Trigger polarity</a></h3>
......
hdl/rtl/wb_gen/fmc_adc_100Ms_csr.wb
View file @ afdb9516
......@@ -278,6 +278,52 @@ peripheral {
clock = "fs_clk_i";
};
field {
align = 16;
name = "Forward external trigger to trigger out";
description = "0: disable\n1: enable";
prefix = "fwd_ext";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
align = 8;
name = "Forward channel 1 internal threshold trigger to trigger out";
description = "0: disable\n1: enable";
prefix = "fwd_ch1";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Forward channel 2 internal threshold trigger to trigger out";
description = "0: disable\n1: enable";
prefix = "fwd_ch2";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Forward channel 3 internal threshold trigger to trigger out";
description = "0: disable\n1: enable";
prefix = "fwd_ch3";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Forward channel 4 internal threshold trigger to trigger out";
description = "0: disable\n1: enable";
prefix = "fwd_ch4";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
......
hdl/rtl/wb_gen/fmc_adc_alt_trigout.cheby
View file @ afdb9516
......@@ -27,32 +27,6 @@ memory-map:
name: ts_present
description: Set when the timestamp fifo is not empty
range: 8
- reg:
name: enable
description: Enable register
access: rw
width: 32
children:
- field:
name: ch1_enable
description: Enable channel 1 trigger
range: 0
- field:
name: ch2_enable
description: Enable channel 2 trigger
range: 1
- field:
name: ch3_enable
description: Enable channel 3 trigger
range: 2
- field:
name: ch4_enable
description: Enable channel 4 trigger
range: 3
- field:
name: ext_enable
description: Enable external trigger
range: 8
- reg:
name: ts_mask_sec
description: Time (seconds) of the last event
......@@ -86,7 +60,7 @@ memory-map:
- reg:
name: ts_cycles
description: Cycles part of timestamp fifo.
comment: Reading this register discard the entry
comment: Reading this register discards the entry
width: 32
access: ro
x-hdl:
......
hdl/rtl/wb_gen/fmc_adc_alt_trigout.h
View file @ afdb9516
......@@ -8,14 +8,6 @@
#define ALT_TRIGOUT_WR_VALID 0x4UL
#define ALT_TRIGOUT_TS_PRESENT 0x100UL
/* Enable register */
#define ALT_TRIGOUT_ENABLE 0x4UL
#define ALT_TRIGOUT_CH1_ENABLE 0x1UL
#define ALT_TRIGOUT_CH2_ENABLE 0x2UL
#define ALT_TRIGOUT_CH3_ENABLE 0x4UL
#define ALT_TRIGOUT_CH4_ENABLE 0x8UL
#define ALT_TRIGOUT_EXT_ENABLE 0x100UL
/* Time (seconds) of the last event */
#define ALT_TRIGOUT_TS_MASK_SEC 0x8UL
#define ALT_TRIGOUT_TS_SEC_MASK 0xffffffffffULL
......@@ -35,8 +27,8 @@ struct alt_trigout {
/* [0x0]: REG (ro) Status register */
uint32_t status;
/* [0x4]: REG (rw) Enable register */
uint32_t enable;
/* padding to: 2 words */
uint32_t __padding_0[1];
/* [0x8]: REG (ro) Time (seconds) of the last event */
uint64_t ts_mask_sec;
......
hdl/rtl/wb_gen/fmc_adc_alt_trigout.html
View file @ afdb9516
......@@ -62,20 +62,13 @@
<td class="td_code">status</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x04</td>
<td>REG</td>
<td><A href="#enable">enable</a></td>
<td class="td_code">enable</td>
<td class="td_code">enable</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x08</td>
<td>REG</td>
<td><A href="#ts_mask_sec">ts_mask_sec</a></td>
<td class="td_code">ts_mask_sec</td>
<td class="td_code">ts_mask_sec</td>
</tr>
<tr class="tr_even">
<tr class="tr_odd">
<td class="td_code">0x10</td>
<td>REG</td>
<td><A href="#ts_cycles">ts_cycles</a></td>
......@@ -192,118 +185,8 @@ wr_valid
ts_present
</b>[<i>ro</i>]: Set when the timestamp fifo is not empty
</ul>
<a name="enable"></a>
<h3><a name="sect_3_2">2.2. enable</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix: </b></td><td class="td_code">alt_trigout_enable</td></tr>
<tr><td><b>HW address: </b></td><td class="td_code">0x4</td></tr>
<tr><td><b>C prefix: </b></td><td class="td_code">enable</td></tr>
<tr><td><b>C offset: </b></td><td class="td_code">0x4</td></tr>
</table>
<p>
Enable register
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit" colspan="1">31</td>
<td class="td_bit" colspan="1">30</td>
<td class="td_bit" colspan="1">29</td>
<td class="td_bit" colspan="1">28</td>
<td class="td_bit" colspan="1">27</td>
<td class="td_bit" colspan="1">26</td>
<td class="td_bit" colspan="1">25</td>
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
<td class="td_bit" colspan="1">22</td>
<td class="td_bit" colspan="1">21</td>
<td class="td_bit" colspan="1">20</td>
<td class="td_bit" colspan="1">19</td>
<td class="td_bit" colspan="1">18</td>
<td class="td_bit" colspan="1">17</td>
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
<td class="td_bit" colspan="1">14</td>
<td class="td_bit" colspan="1">13</td>
<td class="td_bit" colspan="1">12</td>
<td class="td_bit" colspan="1">11</td>
<td class="td_bit" colspan="1">10</td>
<td class="td_bit" colspan="1">9</td>
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">ext_enable</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
<td class="td_bit" colspan="1">6</td>
<td class="td_bit" colspan="1">5</td>
<td class="td_bit" colspan="1">4</td>
<td class="td_bit" colspan="1">3</td>
<td class="td_bit" colspan="1">2</td>
<td class="td_bit" colspan="1">1</td>
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">ch4_enable</td>
<td class="td_field" colspan="1">ch3_enable</td>
<td class="td_field" colspan="1">ch2_enable</td>
<td class="td_field" colspan="1">ch1_enable</td>
</tr>
</table>
<ul>
<li><b>
ch1_enable
</b>[<i>rw</i>]: Enable channel 1 trigger
<li><b>
ch2_enable
</b>[<i>rw</i>]: Enable channel 2 trigger
<li><b>
ch3_enable
</b>[<i>rw</i>]: Enable channel 3 trigger
<li><b>
ch4_enable
</b>[<i>rw</i>]: Enable channel 4 trigger
<li><b>
ext_enable
</b>[<i>rw</i>]: Enable external trigger
</ul>
<a name="ts_mask_sec"></a>
<h3><a name="sect_3_3">2.3. ts_mask_sec</a></h3>
<h3><a name="sect_3_2">2.2. ts_mask_sec</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix: </b></td><td class="td_code">alt_trigout_ts_mask_sec</td></tr>
<tr><td><b>HW address: </b></td><td class="td_code">0x8</td></tr>
......@@ -461,7 +344,7 @@ ext_mask
</b>[<i>ro</i>]: Set if external trigger
</ul>
<a name="ts_cycles"></a>
<h3><a name="sect_3_4">2.4. ts_cycles</a></h3>
<h3><a name="sect_3_3">2.3. ts_cycles</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix: </b></td><td class="td_code">alt_trigout_ts_cycles</td></tr>
<tr><td><b>HW address: </b></td><td class="td_code">0x10</td></tr>
......
hdl/testbench/fmc_adc_mezzanine/main.sv
View file @ afdb9516
......@@ -40,7 +40,7 @@ module main;
IVHDWishboneMaster Trigout ( clk_sys, rst_n );
wire t_wishbone_slave_data64_out dummy_wb64_out =
'{ack: 1'b1, err: 1'b0, rty: 1'b0, stall: 1'b0, dat: 64'bx};
'{ack: 1'b1, err: 1'b0, rty: 1'b0, stall: 1'b0, dat: 64'bx};
fmc_adc_mezzanine
#(
......@@ -51,18 +51,18 @@ module main;
.wb_csr_slave_i (Host.out),
.wb_csr_slave_o (Host.in),
.wb_ddr_clk_i (clk_sys),
.wb_ddr_rst_n_i (rst_n),
.wb_ddr_rst_n_i (rst_n),
.wb_ddr_master_i (dummy_wb64_out),
.wb_ddr_master_o (),
.wb_ddr_master_o (),
.ddr_wr_fifo_empty_i (),
.trig_irq_o (),
.acq_end_irq_o (),
.eic_irq_o (),
.acq_cfg_ok_o (),
.wb_trigin_slave_i (Trigin.out),
.wb_trigin_slave_o (Trigin.in),
.wb_trigout_slave_i (Trigout.out),
.wb_trigout_slave_o (Trigout.in),
.wb_trigin_slave_i (Trigin.out),
.wb_trigin_slave_o (Trigin.in),
.wb_trigout_slave_i (Trigout.out),
.wb_trigout_slave_o (Trigout.in),
.ext_trigger_p_i (ext_trig),
.ext_trigger_n_i (~ext_trig),
.adc_dco_p_i (adc0_dco),
......@@ -235,14 +235,16 @@ module main;
expected = 0;
if (val != expected)
$fatal (1, "trigout status error (got 0x%8x, expected 0x%8x).",
val, expected);
val, expected);
// Save all triggers in trigout fifo.
trigout_acc.write(`ADDR_ALT_TRIGOUT_CTRL, ( `ALT_TRIGOUT_CH1_ENABLE
| `ALT_TRIGOUT_CH2_ENABLE
| `ALT_TRIGOUT_CH3_ENABLE
| `ALT_TRIGOUT_CH4_ENABLE
| `ALT_TRIGOUT_EXT_ENABLE));
acc.read(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
val |= `FMC_ADC_100MS_CSR_TRIG_EN_FWD_EXT
| `FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH1
| `FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH2
| `FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH3
| `FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH4;
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
#1us;
......@@ -288,9 +290,10 @@ module main;
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h0000008);
// FMC-ADC core trigger configuration
val = (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_SW_OFFSET) |
(1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_CH1_OFFSET) |
(1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_CH3_OFFSET);
acc.read(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
val |= (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_SW_OFFSET) |
(1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_CH1_OFFSET) |
(1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_CH3_OFFSET);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
$display("<%t> START ACQ 3", $realtime);
......@@ -311,18 +314,19 @@ module main;
// set time trigger
acc.write(`TAG_BASE + `ADDR_TIMETAG_CORE_TIME_TRIG_SECONDS_UPPER,
'h00000032); // timetag core seconds high
'h00000032); // timetag core seconds high
acc.write(`TAG_BASE + `ADDR_TIMETAG_CORE_TIME_TRIG_SECONDS_LOWER,
'h00005a34); // timetag core seconds low
'h00005a34); // timetag core seconds low
acc.write(`TAG_BASE + `ADDR_TIMETAG_CORE_TIME_TRIG_COARSE,
'h00000e00); // timetag core ticks
'h00000e00); // timetag core ticks
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES, 'h00000010);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES, 'h00000080);
// FMC-ADC core trigger configuration
val = (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_TIME_OFFSET) |
(1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_EXT_OFFSET);
acc.read(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
val |= (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_TIME_OFFSET) |
(1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_EXT_OFFSET);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_EXT_TRIG_DLY, 3);
......@@ -354,7 +358,8 @@ module main;
// set time trigger
trigin_acc.write(`ADDR_ALT_TRIGIN_SECONDS + 0, 'h00000032);
trigin_acc.write(`ADDR_ALT_TRIGIN_SECONDS + 4, 'h00005a34);
trigin_acc.write(`ADDR_ALT_TRIGIN_CYCLES, 'h00001000);
acc.read(`TAG_BASE + `ADDR_TIMETAG_CORE_TIME_TRIG_COARSE, val);
trigin_acc.write(`ADDR_ALT_TRIGIN_CYCLES, val + 'h00001000);
trigin_acc.write(`ADDR_ALT_TRIGIN_CTRL, `ALT_TRIGIN_CTRL_ENABLE);
trigin_acc.read(`ADDR_ALT_TRIGIN_CTRL, val);
......@@ -362,7 +367,7 @@ module main;
if (val != expected)
begin
$fatal (1, "trigin ctrl error (got 0x%8x, expected 0x%8x).",
val, expected);
val, expected);
end
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES, 'h00000001);
......@@ -386,7 +391,7 @@ module main;
if (val != expected)
begin
$fatal (1, "trigin ctrl error (got 0x%8x, expected 0x%8x).",
val, expected);
val, expected);
end
$display("<%t> END ACQ 5", $realtime);
......@@ -394,18 +399,18 @@ module main;
$display("<%t> read trigout fifo", $realtime);
while (1) begin
uint64_t sec_hi, sec_lo, cycs;
uint64_t sec_hi, sec_lo, cycs;
trigout_acc.read(`ADDR_ALT_TRIGOUT_STATUS, val);
if (!(val & `ALT_TRIGOUT_TS_PRESENT))
break;
trigout_acc.read(`ADDR_ALT_TRIGOUT_STATUS, val);
if (!(val & `ALT_TRIGOUT_TS_PRESENT))
break;
trigout_acc.read(`ADDR_ALT_TRIGOUT_TS_MASK_SEC + 0, sec_hi);
trigout_acc.read(`ADDR_ALT_TRIGOUT_TS_MASK_SEC + 4, sec_lo);
trigout_acc.read(`ADDR_ALT_TRIGOUT_TS_CYCLES, cycs);
trigout_acc.read(`ADDR_ALT_TRIGOUT_TS_MASK_SEC + 0, sec_hi);
trigout_acc.read(`ADDR_ALT_TRIGOUT_TS_MASK_SEC + 4, sec_lo);
trigout_acc.read(`ADDR_ALT_TRIGOUT_TS_CYCLES, cycs);
$display("trigout TS: 0x%16x 0x%8x",
((sec_hi << 32) | sec_lo), cycs);
$display("trigout TS: 0x%16x 0x%8x",
((sec_hi << 32) | sec_lo), cycs);
end;
#1us;
......
hdl/testbench/include/fmc_adc_100Ms_csr.v
View file @ afdb9516
......@@ -56,6 +56,16 @@
`define FMC_ADC_100MS_CSR_TRIG_EN_CH3 32'h00000400
`define FMC_ADC_100MS_CSR_TRIG_EN_CH4_OFFSET 11
`define FMC_ADC_100MS_CSR_TRIG_EN_CH4 32'h00000800
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_EXT_OFFSET 16
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_EXT 32'h00010000
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH1_OFFSET 24
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH1 32'h01000000
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH2_OFFSET 25
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH2 32'h02000000
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH3_OFFSET 26
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH3 32'h04000000
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH4_OFFSET 27
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH4 32'h08000000
`define ADDR_FMC_ADC_100MS_CSR_TRIG_POL 10'h10
`define FMC_ADC_100MS_CSR_TRIG_POL_EXT_OFFSET 0
`define FMC_ADC_100MS_CSR_TRIG_POL_EXT 32'h00000001
......
hdl/testbench/include/fmc_adc_alt_trigout.v
View file @ afdb9516
......@@ -8,17 +8,6 @@
`define ALT_TRIGOUT_WR_VALID 'h4
`define ALT_TRIGOUT_TS_PRESENT_OFFSET 8
`define ALT_TRIGOUT_TS_PRESENT 'h100
`define ADDR_ALT_TRIGOUT_ENABLE 'h4
`define ALT_TRIGOUT_CH1_ENABLE_OFFSET 0
`define ALT_TRIGOUT_CH1_ENABLE 'h1
`define ALT_TRIGOUT_CH2_ENABLE_OFFSET 1
`define ALT_TRIGOUT_CH2_ENABLE 'h2
`define ALT_TRIGOUT_CH3_ENABLE_OFFSET 2
`define ALT_TRIGOUT_CH3_ENABLE 'h4
`define ALT_TRIGOUT_CH4_ENABLE_OFFSET 3
`define ALT_TRIGOUT_CH4_ENABLE 'h8
`define ALT_TRIGOUT_EXT_ENABLE_OFFSET 8
`define ALT_TRIGOUT_EXT_ENABLE 'h100
`define ADDR_ALT_TRIGOUT_TS_MASK_SEC 'h8
`define ALT_TRIGOUT_TS_SEC_OFFSET 0
`define ALT_TRIGOUT_TS_SEC 'hffffffffff
......
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