Skip to content

F
FMC ADC 100M 14b 4cha - Gateware
Commit 24949efe authored by Dimitris Lampridis's avatar Dimitris Lampridis
1 Browse files
Options

[doc] Clarify ADC channel data output format. Closes #9

parent 3bf751db
Hide whitespace changes
Inline Side-by-side
Showing with 19 additions and 4 deletions
doc/manual/fmcadc100m14b4cha_gateware_manual.in
View file @ 24949efe
......@@ -735,6 +735,13 @@ The frame rate signal is used to align the de-serialiser to data words.
The four channel data (16-bit) are concatenated together to form a 64-bit vector.
As shown in @ref{fig:ltc2174_mode}, the two LSB bits of a data word are always set to zero.
@strong{Important:} Upon reset the ADC defaults to ``offset binary''
representation for the channel data. However, the ADC core expects
``two's complement''. Therefore, it is important to change the
relevant configuration register in the ADC itself. When using the
provided FMC-ADC driver, this is done automatically during driver
initialisation.
@c ==========================================================================
@section Control and Status Registers
......
hdl/rtl/fmc_adc_100Ms_csr.cheby
View file @ 24949efe
......@@ -442,7 +442,9 @@ memory-map:
range: 15-0
description: Channel 1 current ADC value
comment: |
Current ADC raw value. The format is binary two\'s complement.
Current ADC raw value. The format depends on ADC configuration; Upon reset, the ADC is
configured for "offset binary". The FMC-ADC driver when loaded, will change this to
binary two\'s complement.
- reg:
name: ch1_calib
address: 0x00000088
......@@ -539,7 +541,9 @@ memory-map:
range: 15-0
description: Channel 2 current ACD value
comment: |
Current ADC raw value. The format is binary two\'s complement.
Current ADC raw value. The format depends on ADC configuration; Upon reset, the ADC is
configured for "offset binary". The FMC-ADC driver when loaded, will change this to
binary two\'s complement.
- reg:
name: ch2_calib
address: 0x000000c8
......@@ -636,7 +640,9 @@ memory-map:
range: 15-0
description: Channel 3 current ADC value
comment: |
Current ADC raw value. The format is binary two\'s complement.
Current ADC raw value. The format depends on ADC configuration; Upon reset, the ADC is
configured for "offset binary". The FMC-ADC driver when loaded, will change this to
binary two\'s complement.
- reg:
name: ch3_calib
address: 0x00000108
......@@ -733,7 +739,9 @@ memory-map:
range: 15-0
description: Channel 4 current ADC value
comment: |
Current ADC raw value. The format is binary two\'s complement.
Current ADC raw value. The format depends on ADC configuration; Upon reset, the ADC is
configured for "offset binary". The FMC-ADC driver when loaded, will change this to
binary two\'s complement.
- reg:
name: ch4_calib
address: 0x00000148
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment