Avoid multiple definition of the same unit.
Avoid warnings from hdlmake.

2.0.0 - 2020-07-24
=================
https://www.ohwr.org/project/ddr3-sp6-core/tree/v2.0.0

Added
-----
- Generics to control granularity of Wishbone ports
- Option for active-high reset
- Micron DD3 BFM
- SystemVerilog testbench

Changed
-------
- Complete rewrite of the Wishbone interface to improve compatibility, performance and code readability

Removed
-------
- Unused file ``rtl/ddr3_ctrl_wb_single.vhd``

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

This is done in order to:

1. Fix incompatibilities with pipelined wishbone
2. Improve performance
3, Improve code readability

ddr3_ctrl_wb: no need to check for wb_cyc when checking for wb_stb_valid, the latter includes the former.

hdlmake does not allow by default local variables in included Manifest.py files. So, when this core is included in a bigger project (such as FMC-ADC), it should not have any local variables in its local Manifest.py file. Tested with SPEC and SVEC versions of FMC-ADC, works.

Command strobe should asserted even if it is already 1.

Was not porperly generating the command strobe to ddr interface in case
of wishbone block transfers.

The command enable signal was not properly generated for single read cycle.

git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@110 739e5516-d4a2-47df-ba96-5610c1fa693f

git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@109 739e5516-d4a2-47df-ba96-5610c1fa693f

git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@108 739e5516-d4a2-47df-ba96-5610c1fa693f

Modify Manifests accordingly.



git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@107 739e5516-d4a2-47df-ba96-5610c1fa693f

git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@106 739e5516-d4a2-47df-ba96-5610c1fa693f

git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@105 739e5516-d4a2-47df-ba96-5610c1fa693f

git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@104 739e5516-d4a2-47df-ba96-5610c1fa693f

This is to allow different configuration (FPGA/memory chip) for the same port.
Add re-generated core with new names.



git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@103 739e5516-d4a2-47df-ba96-5610c1fa693f

git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@102 739e5516-d4a2-47df-ba96-5610c1fa693f