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DDR3 controller for Spartan6
Commit 81eb9449 authored by Tristan Gingold's avatar Tristan Gingold
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ddr3_ctrl_wb: add/remove comments.

parent d78b2b5c
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Showing with 12 additions and 23 deletions
hdl/rtl/ddr3_ctrl_wb.vhd
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......@@ -112,6 +112,10 @@ entity ddr3_ctrl_wb is
----------------------------------------------------------------------------
-- Wishbone bus port
----------------------------------------------------------------------------
-- Restrictions:
-- * pipelined only
-- * cannot mix read and writes during the same cycle (cyc=1)
-- * must use consecutive addresses during the same cycle (cyc=1)
wb_clk_i : in std_logic;
wb_sel_i : in std_logic_vector(g_MASK_SIZE - 1 downto 0);
wb_cyc_i : in std_logic;
......@@ -123,14 +127,9 @@ entity ddr3_ctrl_wb is
wb_ack_o : out std_logic;
wb_stall_o : out std_logic
);
end entity ddr3_ctrl_wb;
--==============================================================================
--! Architecure declaration for ddr3_ctrl_wb
--==============================================================================
architecture rtl of ddr3_ctrl_wb is
------------------------------------------------------------------------------
-- Constants declaration
......@@ -165,16 +164,7 @@ architecture rtl of ddr3_ctrl_wb is
signal ddr_wr_mask : std_logic_vector(g_MASK_SIZE - 1 downto 0);
signal ddr_wr_data : std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
signal ddr_rd_en : std_logic;
--==============================================================================
--! Architecure begin
--==============================================================================
begin
------------------------------------------------------------------------------
-- Wishbone interface
------------------------------------------------------------------------------
-- Clocking
ddr_cmd_clk_o <= wb_clk_i;
ddr_wr_clk_o <= wb_clk_i;
......@@ -204,6 +194,7 @@ begin
wb_stb_f_edge <= not(wb_stb_valid) and wb_stb_d;
-- Data inputs
-- Write data to the MCB fifo as long as stb and we are both set.
p_ddr_inputs : process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
......@@ -273,21 +264,25 @@ begin
ddr_burst_cnt <= (others => '0');
else
if (wb_cyc_f_edge = '1') then
-- Be ready for a new burst.
ddr_burst_cnt <= to_unsigned(0, ddr_burst_cnt'length);
elsif (wb_stb_valid = '1') then
-- Increment the burst length for each transaction.
if (ddr_burst_cnt = c_DDR_BURST_LENGTH) then
ddr_burst_cnt <= to_unsigned(1, ddr_burst_cnt'length);
else
ddr_burst_cnt <= ddr_burst_cnt + 1;
end if;
elsif (ddr_burst_cnt = c_DDR_BURST_LENGTH) then
-- New burst.
ddr_burst_cnt <= to_unsigned(0, ddr_burst_cnt'length);
end if;
end if;
end if;
end process p_ddr_burst_cnt;
-- Read enable signal generation
-- Read enable signal generation.
-- Data are available as long as the MCB fifo is not empty.
ddr_rd_en <= not(ddr_rd_empty_i);
-- Data output and ack
......@@ -298,7 +293,8 @@ begin
wb_ack_o <= '0';
wb_data_o <= (others => '0');
else
-- Generates ack signal
-- Generates ack signal (either when data are available from the MCB fifo
-- or when data are written to the MCB fifo)
if (ddr_rd_en = '1') or (ddr_wr_en = '1') then
wb_ack_o <= '1';
else
......@@ -328,8 +324,6 @@ begin
end if;
end if;
end process p_ddr_stall;
--wb_stall_o <= ddr_cmd_full_i or ddr_wr_full_i or ddr_rd_full_i;
-- Assign outputs
ddr_cmd_en_o <= ddr_cmd_en;
......@@ -342,9 +336,4 @@ begin
ddr_wr_data_o <= ddr_wr_data;
ddr_rd_en_o <= ddr_rd_en;
end architecture rtl;
--==============================================================================
--! Architecure end
--==============================================================================
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