Modify bank port type selection default value in the component declaration.

git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@108 739e5516-d4a2-47df-ba96-5610c1fa693f

Modify bank port type selection default value in the component declaration.
git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@108 739e5516-d4a2-47df-ba96-5610c1fa693f
e442e51a · mcattin · b8307a81 · e442e51a
Commit e442e51a authored Aug 09, 2012 by mcattin
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ddr3_ctrl.vhd hdl/rtl/ddr3_ctrl.vhd +2 -2

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--- a/hdl/rtl/ddr3_ctrl.vhd
+++ b/hdl/rtl/ddr3_ctrl.vhd
@@ -51,7 +51,7 @@ entity ddr3_ctrl is

  generic(
    --! Bank and port size selection
-    g_BANK_PORT_SELECT   : string  := "BANK3_32B_32B";
+    g_BANK_PORT_SELECT   : string  := "SPEC_BANK3_32B_32B";
    --! Core's clock period in ps
    g_MEMCLK_PERIOD      : integer := 3000;
    --! If TRUE, uses Xilinx calibration core (Input term, DQS centering)
@@ -297,7 +297,7 @@ architecture rtl of ddr3_ctrl is

  component ddr3_ctrl_wrapper
    generic(
-      g_BANK_PORT_SELECT   : string  := "BANK3_32B_32B";
+      g_BANK_PORT_SELECT   : string  := "SPEC_BANK3_32B_32B";
      g_MEMCLK_PERIOD      : integer := 3000;
      g_CALIB_SOFT_IP      : string  := "TRUE";
      g_MEM_ADDR_ORDER     : string  := "ROW_BANK_COLUMN";