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DDR3 controller for Spartan6
Commit 137e2d48 authored by mcattin's avatar mcattin
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Modify generated core naming to include board reference. 

This is to allow different configuration (FPGA/memory chip) for the same port.
Add re-generated core with new names.



git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@103 739e5516-d4a2-47df-ba96-5610c1fa693f
parent ce769f0f
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hdl/README.txt 0 → 100644
View file @ 137e2d48
Note:
When (re)generating MCB cores, the IBUFG for the clock must be commented out and
bypassed. Otherwise it can cause translation errors (automacically connects it to
a PAD and then complains because the buffer as multi-source!).
The IBUFG instanciation is in the folling file:
<board>/ip_cores/ddr3_ctrl_<board>_bank<nbank>_<nbit0>b_<nbit1>b/user_design/rtl/memc<nbank>_infrastructure.vhd
Diff example:
--***********************************************************************
-- SINGLE_ENDED input clock input buffers
--***********************************************************************
- u_ibufg_sys_clk : IBUFG
- port map (
- I => sys_clk,
- O => sys_clk_ibufg
- );
+ --u_ibufg_sys_clk : IBUFG
+ -- port map (
+ -- I => sys_clk,
+ -- O => sys_clk_ibufg
+ -- );
+ sys_clk_ibufg <= sys_clk;
end generate;
--***************************************************************************
hdl/rtl/Manifest.py
View file @ 137e2d48
......@@ -4,9 +4,11 @@ files = ["ddr3_ctrl.vhd",
"ddr3_ctrl_wrapper_pkg.vhd",
"ddr3_ctrl_pkg.vhd"]
modules = {"local" : ["../spec/ip_cores/ddr3_ctrl_bank3_32b_32b/user_design/rtl",
"../spec/ip_cores/ddr3_ctrl_bank3_64b_32b/user_design/rtl",
"../svec/ip_cores/ddr3_ctrl_bank4_32b_32b/user_design/rtl",
"../svec/ip_cores/ddr3_ctrl_bank4_64b_32b/user_design/rtl",
"../svec/ip_cores/ddr3_ctrl_bank5_32b_32b/user_design/rtl",
"../svec/ip_cores/ddr3_ctrl_bank5_64b_32b/user_design/rtl"]}
modules = {"local" : ["../spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl",
"../spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl",
"../svec/ip_cores/ddr3_ctrl_svec_bank4_32b_32b/user_design/rtl",
"../svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl",
"../svec/ip_cores/ddr3_ctrl_svec_bank5_32b_32b/user_design/rtl",
"../svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl",
"../vfc/ip_cores/ddr3_ctrl_vfc_bank1_32b_32b/user_design/rtl",
"../vfc/ip_cores/ddr3_ctrl_vfc_bank1_64b_32b/user_design/rtl"]}
hdl/rtl/ddr3_ctrl_wrapper.vhd
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This diff is collapsed.
hdl/rtl/ddr3_ctrl_wrapper_pkg.vhd
View file @ 137e2d48
......@@ -50,7 +50,7 @@ package ddr3_ctrl_wrapper_pkg is
--============================================================================
--! Components declaration
--============================================================================
component ddr3_ctrl_bank3_32b_32b
component ddr3_ctrl_spec_bank3_32b_32b
generic
(C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
......@@ -140,9 +140,9 @@ package ddr3_ctrl_wrapper_pkg is
c3_p1_rd_overflow : out std_logic;
c3_p1_rd_error : out std_logic
);
end component ddr3_ctrl_bank3_32b_32b;
end component ddr3_ctrl_spec_bank3_32b_32b;
component ddr3_ctrl_bank3_64b_32b
component ddr3_ctrl_spec_bank3_64b_32b
generic
(C3_P0_MASK_SIZE : integer := 8;
C3_P0_DATA_PORT_SIZE : integer := 64;
......@@ -232,9 +232,9 @@ package ddr3_ctrl_wrapper_pkg is
c3_p1_rd_overflow : out std_logic;
c3_p1_rd_error : out std_logic
);
end component ddr3_ctrl_bank3_64b_32b;
end component ddr3_ctrl_spec_bank3_64b_32b;
component ddr3_ctrl_bank4_32b_32b
component ddr3_ctrl_svec_bank4_32b_32b
generic
(C4_P0_MASK_SIZE : integer := 4;
C4_P0_DATA_PORT_SIZE : integer := 32;
......@@ -324,9 +324,9 @@ package ddr3_ctrl_wrapper_pkg is
c4_p1_rd_overflow : out std_logic;
c4_p1_rd_error : out std_logic
);
end component ddr3_ctrl_bank4_32b_32b;
end component ddr3_ctrl_svec_bank4_32b_32b;
component ddr3_ctrl_bank4_64b_32b
component ddr3_ctrl_svec_bank4_64b_32b
generic
(C4_P0_MASK_SIZE : integer := 8;
C4_P0_DATA_PORT_SIZE : integer := 64;
......@@ -416,9 +416,9 @@ package ddr3_ctrl_wrapper_pkg is
c4_p1_rd_overflow : out std_logic;
c4_p1_rd_error : out std_logic
);
end component ddr3_ctrl_bank4_64b_32b;
end component ddr3_ctrl_svec_bank4_64b_32b;
component ddr3_ctrl_bank5_32b_32b
component ddr3_ctrl_svec_bank5_32b_32b
generic
(C5_P0_MASK_SIZE : integer := 4;
C5_P0_DATA_PORT_SIZE : integer := 32;
......@@ -508,9 +508,9 @@ package ddr3_ctrl_wrapper_pkg is
c5_p1_rd_overflow : out std_logic;
c5_p1_rd_error : out std_logic
);
end component ddr3_ctrl_bank5_32b_32b;
end component ddr3_ctrl_svec_bank5_32b_32b;
component ddr3_ctrl_bank5_64b_32b
component ddr3_ctrl_svec_bank5_64b_32b
generic
(C5_P0_MASK_SIZE : integer := 8;
C5_P0_DATA_PORT_SIZE : integer := 64;
......@@ -600,7 +600,7 @@ package ddr3_ctrl_wrapper_pkg is
c5_p1_rd_overflow : out std_logic;
c5_p1_rd_error : out std_logic
);
end component ddr3_ctrl_bank5_64b_32b;
end component ddr3_ctrl_svec_bank5_64b_32b;
end ddr3_ctrl_wrapper_pkg;
......
hdl/spec/ip_cores/coregen.cgc
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This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b.gise 0 → 100644
View file @ 137e2d48
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="ddr3_ctrl_spec_bank3_32b_32b.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema"/>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b.vho 0 → 100644
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hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b.xco 0 → 100644
View file @ 137e2d48
##############################################################
#
# Xilinx Core Generator version 13.3
# Date: Wed Jul 11 09:32:59 2012
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:mig:3.9
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT MIG_Virtex-6_and_Spartan-6 family Xilinx,_Inc. 3.9
# END Select
# BEGIN Parameters
CSET component_name=ddr3_ctrl_spec_bank3_32b_32b
CSET xml_input_file=./ddr3_ctrl_spec_bank3_32b_32b/user_design/mig.prj
# END Parameters
GENERATE
# CRC: 8651ae82
hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b.xise 0 → 100644
View file @ 137e2d48
This diff is collapsed.
hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/example_design/datasheet.txt 0 → 100644
View file @ 137e2d48
CORE Generator Options:
Target Device : xc6slx45t-fgg484
Speed Grade : -3
HDL : vhdl
Synthesis Tool : Foundation_ISE
MIG Output Options:
Component Name : ddr3_ctrl_spec_bank3_32b_32b
No of Controllers : 1
Hardware Test Bench : enabled
/*******************************************************/
/* Controller 3 */
/*******************************************************/
Controller Options :
Memory : DDR3_SDRAM
Interface : NATIVE
Design Clock Frequency : 3000 ps (333.33 MHz)
Memory Type : Components
Memory Part : MT41J128M16XX-15E
Equivalent Part(s) : MT41J128M16HA-15E
Row Address : 14
Column Address : 10
Bank Address : 3
Data Mask : enabled
Memory Options :
Burst Length : 8(00)
CAS Latency : 6
TDQS enable : Disabled
DLL Enable : Enable
Write Leveling Enable : Disabled
Output Drive Strength : RZQ/6
Additive Latency (AL) : 0
RTT (nominal) - ODT : RZQ/4
Auto Self Refresh : Enabled
CAS write latency : 5
Partial-Array Self Refresh : Full Array
High Temparature Self Refresh Rate : Normal
User Interface Parameters :
Configuration Type : Two 32-bit bi-directional and four 32-bit unidirectional ports
Ports Selected : Port0, Port1
Memory Address Mapping : ROW_BANK_COLUMN
Arbitration Algorithm : Round Robin
Arbitration :
Time Slot0 : 01
Time Slot1 : 10
Time Slot2 : 01
Time Slot3 : 10
Time Slot4 : 01
Time Slot5 : 10
Time Slot6 : 01
Time Slot7 : 10
Time Slot8 : 01
Time Slot9 : 10
Time Slot10: 01
Time Slot11: 10
FPGA Options :
Class for Address and Control : II
Class for Data : II
Memory Interface Pin Termination : EXTERN_TERM
DQ/DQS : 25 Ohms
Bypass Calibration : enabled
Debug Signals for Memory Controller : Disable
Input Clock Type : Single-Ended
\ No newline at end of file
hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/example_design/mig.prj 0 → 100644
View file @ 137e2d48
<?xml version="1.0" encoding="UTF-8"?>
<Project NoOfControllers="1" >
<ModuleName>ddr3_ctrl_spec_bank3_32b_32b</ModuleName>
<TargetFPGA>xc6slx45t-fgg484/-3</TargetFPGA>
<Version>3.9</Version>
<Controller number="3" >
<MemoryDevice>DDR3_SDRAM/Components/MT41J128M16XX-15E</MemoryDevice>
<TimePeriod>3000</TimePeriod>
<EnableVoltageRange>0</EnableVoltageRange>
<DataMask>1</DataMask>
<CustomPart>FALSE</CustomPart>
<NewPartName></NewPartName>
<RowAddress>14</RowAddress>
<ColAddress>10</ColAddress>
<BankAddress>3</BankAddress>
<TimingParameters>
<Parameters twtr="7.5" trefi="7.8" twr="15" trtp="7.5" trfc="160" trp="13.5" tras="36" trcd="13.5" />
</TimingParameters>
<mrBurstLength name="Burst Length" >8(00)</mrBurstLength>
<mrCasLatency name="CAS Latency" >6</mrCasLatency>
<emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
<emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/6</emrOutputDriveStrength>
<emrRTT name="RTT (nominal) - ODT" >RZQ/4</emrRTT>
<emrPosted name="Additive Latency (AL)" >0</emrPosted>
<emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
<emrDQS name="TDQS enable" >Disabled</emrDQS>
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
<mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
<mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
<PortInterface>NATIVE,NATIVE,NATIVE,NATIVE,NATIVE,NATIVE</PortInterface>
<Class>Class II</Class>
<DataClass>Class II</DataClass>
<InputPinTermination>EXTERN_TERM</InputPinTermination>
<DataTermination>25 Ohms</DataTermination>
<CalibrationRowAddress></CalibrationRowAddress>
<CalibrationColumnAddress></CalibrationColumnAddress>
<CalibrationBankAddress></CalibrationBankAddress>
<SystemClock>Single-Ended</SystemClock>
<BypassCalibration>1</BypassCalibration>
<DebugSignals>Disable</DebugSignals>
<SystemClock>Single-Ended</SystemClock>
<Configuration>Two 32-bit bi-directional and four 32-bit unidirectional ports</Configuration>
<RzqPin>M7</RzqPin>
<ZioPin>W4</ZioPin>
<PortsSelected>Port0,Port1</PortsSelected>
<PortDirections>Bi-directional,Bi-directional,none,none,none,none</PortDirections>
<UserMemoryAddressMap>ROW_BANK_COLUMN</UserMemoryAddressMap>
<ArbitrationAlgorithm>Round Robin</ArbitrationAlgorithm>
<TimeSlot0>01</TimeSlot0>
<TimeSlot1>10</TimeSlot1>
<TimeSlot2>01</TimeSlot2>
<TimeSlot3>10</TimeSlot3>
<TimeSlot4>01</TimeSlot4>
<TimeSlot5>10</TimeSlot5>
<TimeSlot6>01</TimeSlot6>
<TimeSlot7>10</TimeSlot7>
<TimeSlot8>01</TimeSlot8>
<TimeSlot9>10</TimeSlot9>
<TimeSlot10>01</TimeSlot10>
<TimeSlot11>10</TimeSlot11>
</Controller>
</Project>
hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/example_design/par/create_ise.sh 0 → 100755
View file @ 137e2d48
#!/bin/csh -f
#*****************************************************************************
# (c) Copyright 2009 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# ****************************************************************************
# ____ ____
# / /\/ /
# /___/ \ / Vendor : Xilinx
# \ \ \/ Version : 3.9
# \ \ Application : MIG
# / / Filename : create_ise.bat
# /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:57 $
# \ \ / \ Date Created : Fri Feb 06 2009
# \___\/\___\
#
# Device : Spartan-6
# Design Name : DDR/DDR2/DDR3/LPDDR
# Purpose : Batch file to run PAR through ISE
# Reference :
# Revision History :
# ****************************************************************************
./rem_files.sh
xtclsh set_ise_prop.tcl
hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/example_design/par/icon_coregen.xco 0 → 100644
View file @ 137e2d48
##############################################################
#
# Xilinx Core Generator version 11.1
# Date: Wed Mar 11 07:09:11 2009
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = vhdl
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = False
SET simulationfiles = Structural
SET speedgrade = -3
SET verilogsim = False
SET vhdlsim = False
# END Project Options
# BEGIN Select
SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.04.a
# END Select
# BEGIN Parameters
CSET component_name=icon
CSET enable_jtag_bufg=true
CSET number_control_ports=2
CSET use_ext_bscan=false
CSET use_softbscan=false
CSET use_unused_bscan=false
CSET user_scan_chain=USER1
# END Parameters
GENERATE
# CRC: 7da1f376
hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/example_design/par/ila_coregen.xco 0 → 100644
View file @ 137e2d48
##############################################################
#
# Xilinx Core Generator version 11.1
# Date: Wed Mar 11 06:55:40 2009
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = False
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = vhdl
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = False
SET simulationfiles = Structural
SET speedgrade = -3
SET verilogsim = False
SET vhdlsim = False
# END Project Options
# BEGIN Select
SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.03.a
# END Select
# BEGIN Parameters
CSET component_name=ila
CSET counter_width_1=Disabled
CSET counter_width_10=Disabled
CSET counter_width_11=Disabled
CSET counter_width_12=Disabled
CSET counter_width_13=Disabled
CSET counter_width_14=Disabled
CSET counter_width_15=Disabled
CSET counter_width_16=Disabled
CSET counter_width_2=Disabled
CSET counter_width_3=Disabled
CSET counter_width_4=Disabled
CSET counter_width_5=Disabled
CSET counter_width_6=Disabled
CSET counter_width_7=Disabled
CSET counter_width_8=Disabled
CSET counter_width_9=Disabled
CSET data_port_width=256
CSET data_same_as_trigger=false
CSET enable_storage_qualification=true
CSET enable_trigger_output_port=false
CSET exclude_from_data_storage_1=true
CSET exclude_from_data_storage_10=true
CSET exclude_from_data_storage_11=true
CSET exclude_from_data_storage_12=true
CSET exclude_from_data_storage_13=true
CSET exclude_from_data_storage_14=true
CSET exclude_from_data_storage_15=true
CSET exclude_from_data_storage_16=true
CSET exclude_from_data_storage_2=true
CSET exclude_from_data_storage_3=true
CSET exclude_from_data_storage_4=true
CSET exclude_from_data_storage_5=true
CSET exclude_from_data_storage_6=true
CSET exclude_from_data_storage_7=true
CSET exclude_from_data_storage_8=true
CSET exclude_from_data_storage_9=true
CSET match_type_1=basic_with_edges
CSET match_type_10=basic
CSET match_type_11=basic
CSET match_type_12=basic
CSET match_type_13=basic
CSET match_type_14=basic
CSET match_type_15=basic
CSET match_type_16=basic
CSET match_type_2=basic
CSET match_type_3=basic
CSET match_type_4=basic
CSET match_type_5=basic
CSET match_type_6=basic
CSET match_type_7=basic
CSET match_type_8=basic
CSET match_type_9=basic
CSET match_units_1=1
CSET match_units_10=1
CSET match_units_11=1
CSET match_units_12=1
CSET match_units_13=1
CSET match_units_14=1
CSET match_units_15=1
CSET match_units_16=1
CSET match_units_2=1
CSET match_units_3=1
CSET match_units_4=1
CSET match_units_5=1
CSET match_units_6=1
CSET match_units_7=1
CSET match_units_8=1
CSET match_units_9=1
CSET max_sequence_levels=1
CSET number_of_trigger_ports=1
CSET sample_data_depth=1024
CSET sample_on=Rising
CSET trigger_port_width_1=2
CSET trigger_port_width_10=8
CSET trigger_port_width_11=8
CSET trigger_port_width_12=8
CSET trigger_port_width_13=8
CSET trigger_port_width_14=8
CSET trigger_port_width_15=8
CSET trigger_port_width_16=8
CSET trigger_port_width_2=8
CSET trigger_port_width_3=8
CSET trigger_port_width_4=8
CSET trigger_port_width_5=8
CSET trigger_port_width_6=8
CSET trigger_port_width_7=8
CSET trigger_port_width_8=8
CSET trigger_port_width_9=8
CSET use_rpms=true
# END Parameters
GENERATE
# CRC: eff89f81
hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/example_design/par/ise_flow.sh 0 → 100755
View file @ 137e2d48
#!/bin/csh -f
#*****************************************************************************
# (c) Copyright 2009 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# ****************************************************************************
# ____ ____
# / /\/ /
# /___/ \ / Vendor : Xilinx
# \ \ \/ Version : 3.9
# \ \ Application : MIG
# / / Filename : ise_flow.bat
# /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:57 $
# \ \ / \ Date Created : Fri Feb 06 2009
# \___\/\___\
#
# Device : Spartan-6
# Design Name : DDR/DDR2/DDR3/LPDDR
# Purpose : Batch file to run PAR through ISE batch mode
# Reference :
# Revision History :
# ****************************************************************************
./rem_files.sh
echo Synthesis Tool: XST
mkdir "../synth/__projnav" > ise_flow_results.txt
mkdir "../synth/xst" >> ise_flow_results.txt
mkdir "../synth/xst/work" >> ise_flow_results.txt
xst -ifn ise_run.txt -ofn mem_interface_top.syr -intstyle ise >> ise_flow_results.txt
ngdbuild -intstyle ise -dd ../synth/_ngo -uc example_top.ucf -p xc6slx45tfgg484-3 example_top.ngc example_top.ngd >> ise_flow_results.txt
map -intstyle ise -detail -w -pr off -c 100 -o example_top_map.ncd example_top.ngd example_top.pcf >> ise_flow_results.txt
par -w -intstyle ise -ol std example_top_map.ncd example_top.ncd example_top.pcf >> ise_flow_results.txt
trce -e 100 example_top.ncd example_top.pcf >> ise_flow_results.txt
bitgen -intstyle ise -f mem_interface_top.ut example_top.ncd >> ise_flow_results.txt
echo done!
hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/example_design/par/ise_run.txt 0 → 100644
View file @ 137e2d48
set -tmpdir ../synth/__projnav
set -xsthdpdir ../synth/xst
run
#Source Parameters
-ifn ../synth/example_top.prj
-ifmt mixed
-iuc No
#Target Parameters
-ofn example_top
-ofmt NGC
-p xc6slx45t-3fgg484
#AXI_ENABLE definition is not required for NATIVE interface
#Source Options
-top example_top
-fsm_extract Yes
-fsm_encoding one-hot
-safe_implementation No
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-rom_style Auto
-shreg_extract Yes
-resource_sharing Yes
-async_to_sync no
-mult_style auto
-register_balancing No
#Target Options
-iobuf Yes
#Max fanout value shouldn't be set below 64 for MCB design
-max_fanout 500
-bufg 16
-register_duplication yes
-optimize_primitives No
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob auto
-equivalent_register_removal yes
#General Options
-opt_mode Speed
-opt_level 1
-lso ../synth/example_top.lso
-keep_hierarchy NO
-netlist_hierarchy as_optimized
-rtlview Yes
-glob_opt allclocknets
-read_cores Yes
-write_timing_constraints No
-cross_clock_analysis No
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-auto_bram_packing No
-slice_utilization_ratio_maxmargin 5
quit
hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/example_design/par/mem_interface_top.ut 0 → 100644
View file @ 137e2d48
-w
-g DebugBitstream:No
-g Binary:no
-g CRC:Enable
-g M2Pin:PullUp
-g ProgPin:PullUp
-g DonePin:PullUp
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullNone
-g UserID:0xFFFFFFFF
-g StartUpClk:CClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Security:None
-g DonePipe:No
-g DriveDone:No
-g ConfigRate:6
hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/example_design/par/readme.txt 0 → 100644
View file @ 137e2d48
::****************************************************************************
:: (c) Copyright 2009 Xilinx, Inc. All rights reserved.
::
:: This file contains confidential and proprietary information
:: of Xilinx, Inc. and is protected under U.S. and
:: international copyright and other intellectual property
:: laws.
::
:: DISCLAIMER
:: This disclaimer is not a license and does not grant any
:: rights to the materials distributed herewith. Except as
:: otherwise provided in a valid license issued to you by
:: Xilinx, and to the maximum extent permitted by applicable
:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
:: (2) Xilinx shall not be liable (whether in contract or tort,
:: including negligence, or under any other theory of
:: liability) for any loss or damage of any kind or nature
:: related to, arising under or in connection with these
:: materials, including for any direct, or any indirect,
:: special, incidental, or consequential loss or damage
:: (including loss of data, profits, goodwill, or any type of
:: loss or damage suffered as a result of any action brought
:: by a third party) even if such damage or loss was
:: reasonably foreseeable or Xilinx had been advised of the
:: possibility of the same.
::
:: CRITICAL APPLICATIONS
:: Xilinx products are not designed or intended to be fail-
:: safe, or for use in any application requiring fail-safe
:: performance, such as life-support or safety devices or
:: systems, Class III medical devices, nuclear facilities,
:: applications related to the deployment of airbags, or any
:: other applications that could lead to death, personal
:: injury, or severe property or environmental damage
:: (individually and collectively, "Critical
:: Applications"). Customer assumes the sole risk and
:: liability of any use of Xilinx products in Critical
:: Applications, subject only to applicable laws and
:: regulations governing limitations on product liability.
::
:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
:: PART OF THIS FILE AT ALL TIMES.
::
::****************************************************************************
:: ____ ____
:: / /\/ /
:: /___/ \ / Vendor : Xilinx
:: \ \ \/ Version : 3.9
:: \ \ Application : MIG
:: / / Filename : readme.txt
:: /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:57 $
:: \ \ / \ Date Created : Fri Feb 06 2009
:: \___\/\___\
::
:: Device : Spartan-6
:: Design Name : DDR/DDR2/DDR3/LPDDR
:: Purpose : Information about par folder
:: Reference :
:: Revision History :
::****************************************************************************
This folder has the batch files to synthesize using XST or Synplify Pro and
implement the design either in "Command Line Mode" or in "GUI Mode".
Steps to run the design using the ise_flow (batch mode):
1. Executing the "ise_flow.bat" file synthesizes the design using XST or
Synplify Pro and does implement the design.
a. First it removes the XST/Synplify Pro report files, implementation
files, supporting scripts, the generated chipscope designs (if
enabled) and the ISE project files (if exist any on previous runs)
b. Synthesizes the design either with XST or Synplicity
c. Implements the design with ISE.
2. After the design is run, it creates ise_flow_results.txt file that will have
the ISE log information.
Steps to run the design using the create_ise (GUI mode - for XST cases only):
1. This file will appear for XST cases only.
2. On executing the "create_ise.bat" file creates "test.xise" project file
and set all the properties of the design selected.
3. The design can be implemented in ISE Projnav GUI by invoking the "test.xise" project file.
4. In Linux operating systems, test.xise project can be invoked by executing the command
'ise test.xise' from the terminal.
Other files in PAR folder :
* "example_top.ucf" file is the constraint file for the design.
It has clock constraints, location constraints and IO standards.
* "mem_interface_top.ut" file has the options for the Configuration file
generation i.e. the "example_top.bit" file to run in batch mode.
* "rem_files.bat" file has all the ISE/Synplify Pro generated report files,
implementation files, supporting scripts, the generated chipscope designs
(if enabled) and the ISE project files.
* "set_ise_prop.tcl" file has all the properties that are to be
set in GUI mode.
* "ise_run.txt" file has synthesis options for the XST tool.
This file is used for batch mode.
* "icon_coregen.xco", "ila_coregen.xco" and "vio_coregen.xco"files are used to
generate ChipScope ila,vio and icon EDIF/NGC files. In order to generate the
EDIF/NGC files, you must execute the following commands before starting
synthesis and PAR.
coregen -b ila_coregen.xco
coregen -b icon_coregen.xco
coregen -b vio_coregen.xco
Note : When you generate the design using "Debug Signals for Memory Controller"
option Enable, the above mentioned ChipScope coregen commands are printed
into ise_flow.bat and create_ise.bat files. The example_top rtl file
will have the design debug signals portmapped to vio and icon
ChipScope modules.
* At the start of a Chip Scope Analyzer project, all of the signals in
every core have generic names. "example_top.cdc" is a file that contains
all the signal names of all cores. Upon importing this file, signal names are
renamed to the specified names in "example_top.cdc" file. This file will work
for the generated designs from MIG. If any of the design parameter values
are changed after generating the design, this file will not work.
For Multiple Controller designs, signal names provided in CDC file are of
the controller that is enabled for Debug in the GUI.
synth folder:
1. mem_interface_top_synp.sdc
2. script_synp.tcl
3. example_top.prj
4. example_top.lso
mem_interface_top_synp.sdc and script_synp.tcl files are being used by
Synplify Pro and example_top.prj and example_top.lso are being used by XST.
hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/example_design/par/rem_files.sh 0 → 100755
View file @ 137e2d48
##!/bin/csh -f
##****************************************************************************
## (c) Copyright 2009 Xilinx, Inc. All rights reserved.
##
## This file contains confidential and proprietary information
## of Xilinx, Inc. and is protected under U.S. and
## international copyright and other intellectual property
## laws.
##
## DISCLAIMER
## This disclaimer is not a license and does not grant any
## rights to the materials distributed herewith. Except as
## otherwise provided in a valid license issued to you by
## Xilinx, and to the maximum extent permitted by applicable
## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
## (2) Xilinx shall not be liable (whether in contract or tort,
## including negligence, or under any other theory of
## liability) for any loss or damage of any kind or nature
## related to, arising under or in connection with these
## materials, including for any direct, or any indirect,
## special, incidental, or consequential loss or damage
## (including loss of data, profits, goodwill, or any type of
## loss or damage suffered as a result of any action brought
## by a third party) even if such damage or loss was
## reasonably foreseeable or Xilinx had been advised of the
## possibility of the same.
##
## CRITICAL APPLICATIONS
## Xilinx products are not designed or intended to be fail-
## safe, or for use in any application requiring fail-safe
## performance, such as life-support or safety devices or
## systems, Class III medical devices, nuclear facilities,
## applications related to the deployment of airbags, or any
## other applications that could lead to death, personal
## injury, or severe property or environmental damage
## (individually and collectively, "Critical
## Applications"). Customer assumes the sole risk and
## liability of any use of Xilinx products in Critical
## Applications, subject only to applicable laws and
## regulations governing limitations on product liability.
##
## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
## PART OF THIS FILE AT ALL TIMES.
##
##****************************************************************************
## ____ ____
## / /\/ /
## /___/ \ / Vendor : Xilinx
## \ \ \/ Version : 3.9
## \ \ Application : MIG
## / / Filename : rem_files.bat
## /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:57 $
## \ \ / \ Date Created : Fri Feb 06 2009
## \___\/\___\
##
## Device : Spartan-6
## Design Name : DDR/DDR2/DDR3/LPDDR
## Purpose : Batch file to remove files generated from ISE
## Reference :
## Revision History :
##****************************************************************************
rm -rf "../synth/__projnav"
rm -rf "../synth/xst"
rm -rf "../synth/_ngo"
rm -rf tmp
rm -rf _xmsgs
rm -rf ila_xdb
rm -rf icon_xdb
rm -rf vio_xdb
rm -rf xlnx_auto_0_xdb
rm -rf vio_xmdf.tcl
rm -rf vio_readme.txt
rm -rf vio_flist.txt
rm -rf vio.xise del
rm -rf vio.xco del
rm -rf vio.ngc del
rm -rf vio.ise del
rm -rf vio.gise del
rm -rf vio.cdc del
rm -rf coregen.cgp
rm -rf coregen.cgc
rm -rf coregen.log
rm -rf ila.cdc
rm -rf ila.gise
rm -rf ila.ise
rm -rf ila.ngc
rm -rf ila.xco
rm -rf ila.xise
rm -rf ila_flist.txt
rm -rf ila_readme.txt
rm -rf ila_xmdf.tcl
rm -rf icon.asy
rm -rf icon.gise
rm -rf icon.ise
rm -rf icon.ncf
rm -rf icon.ngc
rm -rf icon.xco
rm -rf icon.xise
rm -rf icon_flist.txt
rm -rf icon_readme.txt
rm -rf icon_xmdf.tcl
rm -rf ise_flow_results.txt
rm -rf example_top_vhdl.prj
rm -rf mem_interface_top.syr
rm -rf example_top.ngc
rm -rf example_top.ngr
rm -rf example_top_xst.xrpt
rm -rf example_top.bld
rm -rf example_top.ngd
rm -rf example_top_ngdbuild.xrpt
rm -rf example_top_map.map
rm -rf example_top_map.mrp
rm -rf example_top_map.ngm
rm -rf example_top.pcf
rm -rf example_top_map.ncd
rm -rf example_top_map.xrpt
rm -rf example_top_summary.xml
rm -rf example_top_usage.xml
rm -rf example_top.ncd
rm -rf example_top.par
rm -rf example_top.xpi
rm -rf example_top.ptwx
rm -rf example_top.pad
rm -rf example_top.unroutes
rm -rf example_top_pad.csv
rm -rf example_top_pad.txt
rm -rf example_top_par.xrpt
rm -rf example_top.twx
rm -rf example_top.bgn
rm -rf example_top.twr
rm -rf example_top.drc
rm -rf example_top_bitgen.xwbt
rm -rf example_top.bit
# Files and folders generated by create ise
rm -rf test_xdb
rm -rf _xmsgs
rm -rf test.gise
rm -rf test.xise
rm -rf test.xise
# Files and folders generated by ISE through GUI mode
rm -rf _ngo
rm -rf xst
rm -rf example_top.lso
rm -rf example_top.prj
rm -rf example_top.xst
rm -rf example_top.stx
rm -rf example_top_prev_built.ngd
rm -rf test.ntrc_log
rm -rf example_top_guide.ncd
rm -rf example_top.cmd_log
rm -rf example_top_summary.html
rm -rf example_top.ut
rm -rf par_usage_statistics.html
rm -rf usage_statistics_webtalk.html
rm -rf webtalk.log
rm -rf device_usage_statistics.html
hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/example_design/par/set_ise_prop.tcl 0 → 100644
View file @ 137e2d48
project new test.xise
project set "Device Family" "spartan6"
project set "Device" "xc6slx45t"
project set "Package" "fgg484"
project set "Speed Grade" "-3"
project set "Synthesis Tool" "XST (VHDL/Verilog)"
project set "Simulator" "ISim (VHDL/Verilog)"
xfile add "../rtl/example_top.vhd"
xfile add "../rtl/iodrp_controller.vhd"
xfile add "../rtl/iodrp_mcb_controller.vhd"
xfile add "../rtl/mcb_raw_wrapper.vhd"
xfile add "../rtl/mcb_soft_calibration.vhd"
xfile add "../rtl/mcb_soft_calibration_top.vhd"
xfile add "../rtl/memc3_infrastructure.vhd"
xfile add "../rtl/memc3_tb_top.vhd"
xfile add "../rtl/memc3_wrapper.vhd"
xfile add "../rtl/traffic_gen/afifo.vhd"
xfile add "../rtl/traffic_gen/cmd_gen.vhd"
xfile add "../rtl/traffic_gen/cmd_prbs_gen.vhd"
xfile add "../rtl/traffic_gen/data_prbs_gen.vhd"
xfile add "../rtl/traffic_gen/init_mem_pattern_ctr.vhd"
xfile add "../rtl/traffic_gen/mcb_flow_control.vhd"
xfile add "../rtl/traffic_gen/mcb_traffic_gen.vhd"
xfile add "../rtl/traffic_gen/rd_data_gen.vhd"
xfile add "../rtl/traffic_gen/read_data_path.vhd"
xfile add "../rtl/traffic_gen/read_posted_fifo.vhd"
xfile add "../rtl/traffic_gen/sp6_data_gen.vhd"
xfile add "../rtl/traffic_gen/tg_status.vhd"
xfile add "../rtl/traffic_gen/v6_data_gen.vhd"
xfile add "../rtl/traffic_gen/wr_data_gen.vhd"
xfile add "../rtl/traffic_gen/write_data_path.vhd"
xfile add "example_top.ucf"
project set "FSM Encoding Algorithm" "Auto" -process "Synthesize - XST"
project set "Safe Implementation" "No" -process "Synthesize - XST"
project set "FSM Style" "LUT" -process "Synthesize - XST"
project set "RAM Extraction" "True" -process "Synthesize - XST"
project set "RAM Style" "Auto" -process "Synthesize - XST"
project set "ROM Extraction" "True" -process "Synthesize - XST"
project set "ROM Style" "Auto" -process "Synthesize - XST"
project set "Resource Sharing" "True" -process "Synthesize - XST"
project set "Asynchronous To Synchronous" "False" -process "Synthesize - XST"
project set "Register Balancing" "No" -process "Synthesize - XST"
project set "Add I/O Buffers" "True" -process "Synthesize - XST"
project set "Max Fanout" "500" -process "Synthesize - XST"
project set "Number of Clock Buffers" "8" -process "Synthesize - XST"
project set "Register Duplication" "True" -process "Synthesize - XST"
project set "Optimize Instantiated Primitives" "False" -process "Synthesize - XST"
project set "Use Clock Enable" "Yes" -process "Synthesize - XST"
project set "Use Synchronous Set" "Yes" -process "Synthesize - XST"
project set "Use Synchronous Reset" "Yes" -process "Synthesize - XST"
project set "Pack I/O Registers into IOBs" "Auto" -process "Synthesize - XST"
project set "Equivalent Register Removal" "True" -process "Synthesize - XST"
project set "Optimization Goal" "Speed" -process "Synthesize - XST"
project set "Optimization Effort" "Normal" -process "Synthesize - XST"
project set "Library Search Order" "../synth/example_top.lso" -process "Synthesize - XST"
project set "Keep Hierarchy" "Soft" -process "Synthesize - XST"
project set "Netlist Hierarchy" "As Optimized" -process "Synthesize - XST"
project set "Generate RTL Schematic" "Yes" -process "Synthesize - XST"
project set "Global Optimization Goal" "AllClockNets" -process "Synthesize - XST"
project set "Read Cores" "True" -process "Synthesize - XST"
project set "Write Timing Constraints" "False" -process "Synthesize - XST"
project set "Cross Clock Analysis" "False" -process "Synthesize - XST"
project set "Hierarchy Separator" "/" -process "Synthesize - XST"
project set "Bus Delimiter" "<>" -process "Synthesize - XST"
project set "Case" "Maintain" -process "Synthesize - XST"
project set "BRAM Utilization Ratio" "100" -process "Synthesize - XST"
project set "Automatic BRAM Packing" "False" -process "Synthesize - XST"
project set "Pack I/O Registers/Latches into IOBs" "Off" -process Map
project set "Place & Route Effort Level (Overall)" "Standard" -process "Place & Route"
project set "Number of Paths in Error/Verbose Report" "100" -process "Generate Post-Map Static Timing"
project set "Enable Debugging of Serial Mode BitStream" "False" -process "Generate Programming File"
project set "Create Binary Configuration File" "False" -process "Generate Programming File"
project set "Enable Cyclic Redundancy Checking (CRC)" "True" -process "Generate Programming File"
project set "Configuration Rate" "6" -process "Generate Programming File"
project set "Configuration Pin Program" "Pull Up" -process "Generate Programming File"
project set "Configuration Pin Done" "Pull Up" -process "Generate Programming File"
project set "JTAG Pin TCK" "Pull Up" -process "Generate Programming File"
project set "JTAG Pin TDI" "Pull Up" -process "Generate Programming File"
project set "JTAG Pin TDO" "Pull Up" -process "Generate Programming File"
project set "JTAG Pin TMS" "Pull Up" -process "Generate Programming File"
project set "Unused IOB Pins" "Float" -process "Generate Programming File"
project set "UserID Code (8 Digit Hexadecimal)" "0xFFFFFFFF" -process "Generate Programming File"
project set "FPGA Start-Up Clock" "CCLK" -process "Generate Programming File"
project set "Done (Output Events)" "Default (4)" -process "Generate Programming File"
project set "Enable Outputs (Output Events)" "Default (5)" -process "Generate Programming File"
project set "Release Write Enable (Output Events)" "Default (6)" -process "Generate Programming File"
project set "Enable Internal Done Pipe" "False" -process "Generate Programming File"
project set "Drive Done Pin High" "False" -process "Generate Programming File"
project set "Security" "Enable Readback and Reconfiguration" -process "Generate Programming File"
project close
hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/example_design/par/vio_coregen.xco 0 → 100644
View file @ 137e2d48
##############################################################
#
# Xilinx Core Generator version 11.2
# Date: Fri Jun 12 05:42:56 2009
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = False
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = vhdl
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = False
SET simulationfiles = Structural
SET speedgrade = -3
SET verilogsim = False
SET vhdlsim = False
# END Project Options
# BEGIN Select
SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.03.a
# END Select
# BEGIN Parameters
CSET asynchronous_input_port_width=8
CSET asynchronous_output_port_width=7
CSET component_name=vio
CSET enable_asynchronous_input_port=false
CSET enable_asynchronous_output_port=true
CSET enable_synchronous_input_port=false
CSET enable_synchronous_output_port=false
CSET invert_clock_input=false
CSET synchronous_input_port_width=8
CSET synchronous_output_port_width=8
# END Parameters
GENERATE
# CRC: 66fe39ed
hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/example_design/sim/functional/ddr3_ctrl_spec_bank3_32b_32b.prj 0 → 100755
View file @ 137e2d48
vhdl work ../../rtl/example_top.vhd
vhdl work ../../rtl/iodrp_controller.vhd
vhdl work ../../rtl/iodrp_mcb_controller.vhd
vhdl work ../../rtl/mcb_raw_wrapper.vhd
vhdl work ../../rtl/mcb_soft_calibration.vhd
vhdl work ../../rtl/mcb_soft_calibration_top.vhd
vhdl work ../../rtl/memc3_infrastructure.vhd
vhdl work ../../rtl/memc3_tb_top.vhd
vhdl work ../../rtl/memc3_wrapper.vhd
vhdl work ../../rtl/traffic_gen/afifo.vhd
vhdl work ../../rtl/traffic_gen/cmd_gen.vhd
vhdl work ../../rtl/traffic_gen/cmd_prbs_gen.vhd
vhdl work ../../rtl/traffic_gen/data_prbs_gen.vhd
vhdl work ../../rtl/traffic_gen/init_mem_pattern_ctr.vhd
vhdl work ../../rtl/traffic_gen/mcb_flow_control.vhd
vhdl work ../../rtl/traffic_gen/mcb_traffic_gen.vhd
vhdl work ../../rtl/traffic_gen/rd_data_gen.vhd
vhdl work ../../rtl/traffic_gen/read_data_path.vhd
vhdl work ../../rtl/traffic_gen/read_posted_fifo.vhd
vhdl work ../../rtl/traffic_gen/sp6_data_gen.vhd
vhdl work ../../rtl/traffic_gen/tg_status.vhd
vhdl work ../../rtl/traffic_gen/v6_data_gen.vhd
vhdl work ../../rtl/traffic_gen/wr_data_gen.vhd
vhdl work ../../rtl/traffic_gen/write_data_path.vhd
verilog work $XILINX/verilog/src/glbl.v
vhdl work ./sim_tb_top.vhd
verilog work ./ddr3_model_c3.v -d x2Gb -d sg15E -d x16 -i ./
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vhdl work ../rtl/example_top.vhd
vhdl work ../rtl/iodrp_controller.vhd
vhdl work ../rtl/iodrp_mcb_controller.vhd
vhdl work ../rtl/mcb_raw_wrapper.vhd
vhdl work ../rtl/mcb_soft_calibration.vhd
vhdl work ../rtl/mcb_soft_calibration_top.vhd
vhdl work ../rtl/memc3_infrastructure.vhd
vhdl work ../rtl/memc3_tb_top.vhd
vhdl work ../rtl/memc3_wrapper.vhd
vhdl work ../rtl/traffic_gen/afifo.vhd
vhdl work ../rtl/traffic_gen/cmd_gen.vhd
vhdl work ../rtl/traffic_gen/cmd_prbs_gen.vhd
vhdl work ../rtl/traffic_gen/data_prbs_gen.vhd
vhdl work ../rtl/traffic_gen/init_mem_pattern_ctr.vhd
vhdl work ../rtl/traffic_gen/mcb_flow_control.vhd
vhdl work ../rtl/traffic_gen/mcb_traffic_gen.vhd
vhdl work ../rtl/traffic_gen/rd_data_gen.vhd
vhdl work ../rtl/traffic_gen/read_data_path.vhd
vhdl work ../rtl/traffic_gen/read_posted_fifo.vhd
vhdl work ../rtl/traffic_gen/sp6_data_gen.vhd
vhdl work ../rtl/traffic_gen/tg_status.vhd
vhdl work ../rtl/traffic_gen/v6_data_gen.vhd
vhdl work ../rtl/traffic_gen/wr_data_gen.vhd
vhdl work ../rtl/traffic_gen/write_data_path.vhd
hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/example_design/synth/mem_interface_top_synp.sdc 0 → 100644
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# Synplicity, Inc. constraint file
# Written on Mon Jun 27 15:50:39 2005
define_attribute {v:work.example_top} syn_hier {hard}
define_attribute {v:work.iodrp_controller} syn_hier {hard}
define_attribute {v:work.iodrp_mcb_controller} syn_hier {hard}
define_attribute {v:work.mcb_raw_wrapper} syn_hier {hard}
define_attribute {v:work.mcb_soft_calibration} syn_hier {hard}
define_attribute {v:work.mcb_soft_calibration_top} syn_hier {hard}
define_attribute {v:work.memc3_infrastructure} syn_hier {hard}
define_attribute {v:work.memc3_tb_top} syn_hier {hard}
define_attribute {v:work.memc3_wrapper} syn_hier {hard}
define_attribute {v:work.afifo} syn_hier {hard}
define_attribute {v:work.cmd_gen} syn_hier {hard}
define_attribute {v:work.cmd_prbs_gen} syn_hier {hard}
define_attribute {v:work.data_prbs_gen} syn_hier {hard}
define_attribute {v:work.init_mem_pattern_ctr} syn_hier {hard}
define_attribute {v:work.mcb_flow_control} syn_hier {hard}
define_attribute {v:work.mcb_traffic_gen} syn_hier {hard}
define_attribute {v:work.rd_data_gen} syn_hier {hard}
define_attribute {v:work.read_data_path} syn_hier {hard}
define_attribute {v:work.read_posted_fifo} syn_hier {hard}
define_attribute {v:work.sp6_data_gen} syn_hier {hard}
define_attribute {v:work.tg_status} syn_hier {hard}
define_attribute {v:work.v6_data_gen} syn_hier {hard}
define_attribute {v:work.wr_data_gen} syn_hier {hard}
define_attribute {v:work.write_data_path} syn_hier {hard}
# clock Constraints
define_clock -disable -name {memc3_infrastructure_inst} -period 3000 -clockgroup default_clkgroup_1
define_clock -name {memc3_infrastructure_inst.SYS_CLK_INST} -period 3000 -clockgroup default_clkgroup_2
define_clock -disable -name {memc3_infrastructure_inst.u_pll_adv} -period 3000 -clockgroup default_clkgroup_3
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