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DDR3 controller for Spartan6
Commit 0ac0a66d authored by mcattin's avatar mcattin
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Change RZQ pin for SVEC bank5 DDR controller from L25 (V0) to G25 (V1 or higher). 

git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@109 739e5516-d4a2-47df-ba96-5610c1fa693f
parent e442e51a
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Showing with 561 additions and 4411 deletions
hdl/svec/ip_cores/coregen.cgc
View file @ 0ac0a66d
This diff is collapsed.
hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_32b_32b.xco
View file @ 0ac0a66d
##############################################################
#
# Xilinx Core Generator version 13.3
# Date: Wed Jul 11 09:28:46 2012
# Date: Wed Oct 24 09:16:59 2012
#
##############################################################
#
......
hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_32b_32b.xise
View file @ 0ac0a66d
......@@ -425,8 +425,8 @@
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-07-11T11:28:49" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="A344C84F064BCF0FC7CED213D5B849A8" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-10-24T11:17:04" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="4D441D20FD76203EE1D20696BC8E4683" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
......
hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_32b_32b/example_design/mig.prj
View file @ 0ac0a66d
......@@ -41,7 +41,7 @@
<DebugSignals>Disable</DebugSignals>
<SystemClock>Single-Ended</SystemClock>
<Configuration>Two 32-bit bi-directional and four 32-bit unidirectional ports</Configuration>
<RzqPin>L25</RzqPin>
<RzqPin>G25</RzqPin>
<ZioPin>N24</ZioPin>
<PortsSelected>Port0,Port1</PortsSelected>
<PortDirections>Bi-directional,Bi-directional,none,none,none,none</PortDirections>
......
hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_32b_32b/example_design/par/example_top.ucf
View file @ 0ac0a66d
############################################################################
##
## Xilinx, Inc. 2006 www.xilinx.com
## Wed Jul 11 11:28:44 2012
## Wed Oct 24 11:16:55 2012
## Generated by MIG Version 3.9
##
############################################################################
......@@ -163,5 +163,5 @@ NET "mcb5_dram_we_n" LOC = "E26" ;
#a 2R resistor should be connected between RZQand ground, where R is the desired#
#input termination value. Otherwise, RZQ should be left as a no-connect (NC) pin.#
##################################################################################
NET "mcb5_rzq" LOC = "L25" ;
NET "mcb5_rzq" LOC = "G25" ;
hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_32b_32b/user_design/mig.prj
View file @ 0ac0a66d
......@@ -41,7 +41,7 @@
<DebugSignals>Disable</DebugSignals>
<SystemClock>Single-Ended</SystemClock>
<Configuration>Two 32-bit bi-directional and four 32-bit unidirectional ports</Configuration>
<RzqPin>L25</RzqPin>
<RzqPin>G25</RzqPin>
<ZioPin>N24</ZioPin>
<PortsSelected>Port0,Port1</PortsSelected>
<PortDirections>Bi-directional,Bi-directional,none,none,none,none</PortDirections>
......
hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_32b_32b/user_design/par/ddr3_ctrl_svec_bank5_32b_32b.ucf
View file @ 0ac0a66d
############################################################################
##
## Xilinx, Inc. 2006 www.xilinx.com
## Wed Jul 11 11:28:44 2012
## Wed Oct 24 11:16:57 2012
## Generated by MIG Version 3.9
##
############################################################################
......@@ -154,5 +154,5 @@ NET "mcb5_dram_we_n" LOC = "E26" ;
#a 2R resistor should be connected between RZQand ground, where R is the desired#
#input termination value. Otherwise, RZQ should be left as a no-connect (NC) pin.#
##################################################################################
NET "mcb5_rzq" LOC = "L25" ;
NET "mcb5_rzq" LOC = "G25" ;
hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_32b_32b/user_design/rtl/memc5_infrastructure.vhd
View file @ 0ac0a66d
......@@ -165,12 +165,11 @@ begin
--***********************************************************************
-- SINGLE_ENDED input clock input buffers
--***********************************************************************
--u_ibufg_sys_clk : IBUFG
-- port map (
-- I => sys_clk,
-- O => sys_clk_ibufg
-- );
sys_clk_ibufg <= sys_clk;
u_ibufg_sys_clk : IBUFG
port map (
I => sys_clk,
O => sys_clk_ibufg
);
end generate;
--***************************************************************************
......
hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_32b_32b_flist.txt
View file @ 0ac0a66d
......@@ -109,4 +109,3 @@ ddr3_ctrl_svec_bank5_32b_32b.xise
ddr3_ctrl_svec_bank5_32b_32b_flist.txt
ddr3_ctrl_svec_bank5_32b_32b_readme.txt
ddr3_ctrl_svec_bank5_32b_32b_xmdf.tcl
mig.prj
hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b.xco
View file @ 0ac0a66d
##############################################################
#
# Xilinx Core Generator version 13.3
# Date: Wed Jul 11 09:30:45 2012
# Date: Wed Oct 24 09:17:56 2012
#
##############################################################
#
......
hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b.xise
View file @ 0ac0a66d
......@@ -425,8 +425,8 @@
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-07-11T11:30:48" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="61436B67058B3FAB87C8E6934C8648BC" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-10-24T11:17:59" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="6D41C0FB2CB194CF38B4ECDD24FF5A97" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
......
hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/example_design/mig.prj
View file @ 0ac0a66d
......@@ -41,7 +41,7 @@
<DebugSignals>Disable</DebugSignals>
<SystemClock>Single-Ended</SystemClock>
<Configuration>One 64-bit bi-directional and two 32-bit bi-directional ports</Configuration>
<RzqPin>L25</RzqPin>
<RzqPin>G25</RzqPin>
<ZioPin>N24</ZioPin>
<PortsSelected>Port0,Port1</PortsSelected>
<PortDirections>Bi-directional,Bi-directional,none</PortDirections>
......
hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/example_design/par/example_top.ucf
View file @ 0ac0a66d
############################################################################
##
## Xilinx, Inc. 2006 www.xilinx.com
## Wed Jul 11 11:30:42 2012
## Wed Oct 24 11:17:53 2012
## Generated by MIG Version 3.9
##
############################################################################
......@@ -163,5 +163,5 @@ NET "mcb5_dram_we_n" LOC = "E26" ;
#a 2R resistor should be connected between RZQand ground, where R is the desired#
#input termination value. Otherwise, RZQ should be left as a no-connect (NC) pin.#
##################################################################################
NET "mcb5_rzq" LOC = "L25" ;
NET "mcb5_rzq" LOC = "G25" ;
hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/mig.prj
View file @ 0ac0a66d
......@@ -41,7 +41,7 @@
<DebugSignals>Disable</DebugSignals>
<SystemClock>Single-Ended</SystemClock>
<Configuration>One 64-bit bi-directional and two 32-bit bi-directional ports</Configuration>
<RzqPin>L25</RzqPin>
<RzqPin>G25</RzqPin>
<ZioPin>N24</ZioPin>
<PortsSelected>Port0,Port1</PortsSelected>
<PortDirections>Bi-directional,Bi-directional,none</PortDirections>
......
hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/par/ddr3_ctrl_svec_bank5_64b_32b.ucf
View file @ 0ac0a66d
############################################################################
##
## Xilinx, Inc. 2006 www.xilinx.com
## Wed Jul 11 11:30:43 2012
## Wed Oct 24 11:17:54 2012
## Generated by MIG Version 3.9
##
############################################################################
......@@ -154,5 +154,5 @@ NET "mcb5_dram_we_n" LOC = "E26" ;
#a 2R resistor should be connected between RZQand ground, where R is the desired#
#input termination value. Otherwise, RZQ should be left as a no-connect (NC) pin.#
##################################################################################
NET "mcb5_rzq" LOC = "L25" ;
NET "mcb5_rzq" LOC = "G25" ;
hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/memc5_infrastructure.vhd
View file @ 0ac0a66d
......@@ -165,12 +165,11 @@ begin
--***********************************************************************
-- SINGLE_ENDED input clock input buffers
--***********************************************************************
--u_ibufg_sys_clk : IBUFG
-- port map (
-- I => sys_clk,
-- O => sys_clk_ibufg
-- );
sys_clk_ibufg <= sys_clk;
u_ibufg_sys_clk : IBUFG
port map (
I => sys_clk,
O => sys_clk_ibufg
);
end generate;
--***************************************************************************
......
hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b_flist.txt
View file @ 0ac0a66d
......@@ -109,4 +109,3 @@ ddr3_ctrl_svec_bank5_64b_32b.xise
ddr3_ctrl_svec_bank5_64b_32b_flist.txt
ddr3_ctrl_svec_bank5_64b_32b_readme.txt
ddr3_ctrl_svec_bank5_64b_32b_xmdf.tcl
mig.prj
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