layout-v1.0
All issues for this milestone are closed. You may close the milestone now.
Project | Open issues | State | Due date |
---|---|---|---|
FMC-PROFINET | 0 | Open | |
DIOT Zynq Ultrascale-based System Board | 0 | Closed | |
DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier | 0 | Closed |
Unstarted Issues (open and unassigned)
0
Ongoing Issues (open and assigned)
0
Completed Issues (closed)
140
- DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier · Power_Supply_2: can we add an optional pull-up on EN_P1V8_FMC?
- DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier · FPGA_Bank_44-46_48_FMC: Verify schematics note
- DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier · Silkscreen: add hyperlinks
- DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier · Remove 2 unnecessary mounting holes
- DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier · Change J9 to 2.54 mm pitch
- DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier · Add copper balancing pattern on L1 and L12
- DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier · Some return vias are missing
- DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier · Increase clearance between traces and FMC mounting holes
- DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier · Some traces are very close to FPGA heatsink mounting holes
- DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier · L12: P1V8_FMC polygon could be extended to fully cover also the last via
- DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier · L8: STRIP1 polygon accidentally cut with keep-out layer
- DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier · Consider modifying the board stack-up
- DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier · different thickness of DDR lines depending on layer?
- DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier · L3: effective width of FMC_VREFA_M2C and FMC_VREFB_M2C polygons
- DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier · L12: add thermal pads (GND) for IRPS5401 (IC21, IC22)
- DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier · Missing table with layers stackup and total board thickness
- DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier · Restore components designators
- DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier · Acid traps
- DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier · 236 DRC errors, mostly on length matching but also on front panel LEMO collision
- DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier · Backplane MGT vs LVDS lanes routing
- DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier · [FPGA_Bank_66_67_68_DDR] forbidden I/O assignment
- FMC-PROFINET · Consider making core between L6 and L7 thicker
- FMC-PROFINET · The P1V5 and VADJ planes stray unneccessarily
- FMC-PROFINET · The P1V5 plane gets way too thin at certain points
- FMC-PROFINET · The ERTEC IC is missing decoupling capacitors on its Vadj bank
- FMC-PROFINET · L10: expand Vadj plane at X:4962mil Y:4289mil
- FMC-PROFINET · remove acid traps at some pads
- FMC-PROFINET · [L7] create void opening in the Chassis polygon
- FMC-PROFINET · Flash.SchDoc both flash chips have the same enable signals and DQ0..15, this will not work
- FMC-PROFINET · Change test points to a different component with smaller footprint
- FMC-PROFINET · Unify traces thickness
- FMC-PROFINET · Not enough reference planes in the board stack-up
- FMC-PROFINET · Routing for memories
- FMC-PROFINET · [L10] X:5200mil Y:3900mil P3V3A polygon stretch can be removed as it does not connect to anything
- FMC-PROFINET · [L1] X:4653mil Y:4085mil very thin 4mil track to P3V3 decoupling cap
- FMC-PROFINET · external trigger
- FMC-PROFINET · FMC connector: Use separate via for each power pin
- FMC-PROFINET · Provide clean return path by providing each GND pin with its own via to GND plane
- FMC-PROFINET · Remove GND polygons from signal layers
- FMC-PROFINET · RJ45 connector wrong pinout
- FMC-PROFINET · Missing magnetics for RJ45 connectors
- FMC-PROFINET · Analog power rails should be decoupled against AGND
- FMC-PROFINET · Missing decoupling capacitors from ERTEC's (IC16) analog power supply pins
- FMC-PROFINET · Memories should be routed in a fly-by topology
- FMC-PROFINET · DC/DC layout issues
- FMC-PROFINET · [L1] X:4800mil, Y:4100mil mix of tracks and GND polygon create acid traps
- FMC-PROFINET · PCB: URL and OHL text missing
- FMC-PROFINET · Frontpanel: shows XXXXX
- DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier · Consider adding pin swapping groups to the FPGA
- DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier · Remove wires from unused FPGA pins
- DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier · 0R resistors might cause short circuits
- DIOT Zynq Ultrascale-based System Board · [L14] X:124mm Y:30mm move SFP.MGT_Tx_P/N so that it lays fully over continuous GND in L13.
- DIOT Zynq Ultrascale-based System Board · [fpga-pl-mgts] SATA_TX vs SATAC_TX have P/N swapped!
- DIOT Zynq Ultrascale-based System Board · [L1] IC22, IC32 layout
- DIOT Zynq Ultrascale-based System Board · [L1] Switching current loops for IC31/IC30 are not small
- DIOT Zynq Ultrascale-based System Board · larger antipads on gnd and power planes
- DIOT Zynq Ultrascale-based System Board · some nets not connected to the centre of the VIA
- DIOT Zynq Ultrascale-based System Board · verify power polygons
- DIOT Zynq Ultrascale-based System Board · possible cross-talk between L7, L8?
- DIOT Zynq Ultrascale-based System Board · spacing between ESD strip 1 and 2 should be 20mm
- DIOT Zynq Ultrascale-based System Board · check if SFP inserted in the cate will not conflict with the front panel extraction handle
- DIOT Zynq Ultrascale-based System Board · [L14] X:199.75mm Y:25.825mm potentially unrouted net MGT2_RxC_P - consisting of 2 traces barely connected together
- DIOT Zynq Ultrascale-based System Board · stitch board outline with gnd vias wherever possible
- DIOT Zynq Ultrascale-based System Board · maximise decoupling capacitor track widths
- DIOT Zynq Ultrascale-based System Board · various board texts
- DIOT Zynq Ultrascale-based System Board · rework mechanical layers
- DIOT Zynq Ultrascale-based System Board · power plane pullback distance
- DIOT Zynq Ultrascale-based System Board · boot mode function table
- DIOT Zynq Ultrascale-based System Board · component designator position
- DIOT Zynq Ultrascale-based System Board · silkscreen font size
- DIOT Zynq Ultrascale-based System Board · silk to soldermask clearance set to 0
- DIOT Zynq Ultrascale-based System Board · press-fit tooling
- DIOT Zynq Ultrascale-based System Board · FMC mounting holes should be connected to chassis ground (not signal GND)
- DIOT Zynq Ultrascale-based System Board · GND track width for FMC connector
- DIOT Zynq Ultrascale-based System Board · add ground via under DDR chips
- DIOT Zynq Ultrascale-based System Board · "mouse bites" for PCB depanelization
- DIOT Zynq Ultrascale-based System Board · remove thermal relief for press-fit connectors
- DIOT Zynq Ultrascale-based System Board · power via hole size
- DIOT Zynq Ultrascale-based System Board · [L12] diff pair deskew
- DIOT Zynq Ultrascale-based System Board · stitch gnd top and bottom polygons next to DDR chips
- DIOT Zynq Ultrascale-based System Board · polygons on signal layer
- DIOT Zynq Ultrascale-based System Board · P1V8 power plane
- DIOT Zynq Ultrascale-based System Board · connect heat-sink mounting hole to GND
- DIOT Zynq Ultrascale-based System Board · create xsignals between DDR chips for command signal group
- DIOT Zynq Ultrascale-based System Board · polygon pour cutout beneat FPGA and FMC connector
- DIOT Zynq Ultrascale-based System Board · [BSilk] many components have their designators removed
- DIOT Zynq Ultrascale-based System Board · [L14] possible acid traps
- DIOT Zynq Ultrascale-based System Board · [L14] 3 ESD strips on the lower edge are not connected to anything
- DIOT Zynq Ultrascale-based System Board · [L14] check all MGT diff pairs routing to ensure they have smooth corners
- DIOT Zynq Ultrascale-based System Board · [L14] X:194mm Y:53mm: SLOT4.LVDS_8 diff pair with 2 sharp corners while later before vias it's smooth
- DIOT Zynq Ultrascale-based System Board · [L12] X:109mm Y:50mm MGT_CLKREF.CLK_P/N have sharp corners
- DIOT Zynq Ultrascale-based System Board · [multiple layers] Various traces widths used for same class slow signals
- DIOT Zynq Ultrascale-based System Board · [L7] some clock lines near IC4 are missing GND return vias (like it's done for 7_PE_CLK_P/N)
- DIOT Zynq Ultrascale-based System Board · [L5] X:116mm Y:39mm sharp corner on otherwise smooth-cornered transceiver lane
- DIOT Zynq Ultrascale-based System Board · [L5] X:217mm Y:50.5mm: what's the reason to have this via?
- DIOT Zynq Ultrascale-based System Board · [L3] X:193mm Y:45mm 7_SERVMOD_N track touches the via, but barely
- DIOT Zynq Ultrascale-based System Board · [L3] some FMC MGT lanes have 1 sharp edge in otherwise soft-edged routing
- DIOT Zynq Ultrascale-based System Board · [multiple layers] not enough stitching vias on some GND polygons
- DIOT Zynq Ultrascale-based System Board · [multiple layers] not needed polygon pour cutouts?
- DIOT Zynq Ultrascale-based System Board · [L1] X:187mm Y:43mm <n>_SERVMOD_N lines could be router nicer, with equal spacing
- DIOT Zynq Ultrascale-based System Board · [L1] SLOT2.LVDS_6_P/N - part of the diff pair has rounded corners, part has sharp corners
- DIOT Zynq Ultrascale-based System Board · [L1] X:130mm Y:9mm: is there a break between GND polygon and GND pads of IC41?
- DIOT Zynq Ultrascale-based System Board · [L1] not needed tracks cutting thermal reliefs
- DIOT Zynq Ultrascale-based System Board · [L1] possible acid traps
- DIOT Zynq Ultrascale-based System Board · [L1] what is the role of pads e.g. on WR_DAC lines (DIN, SYNC1, SYNC2, SCLK)?
- DIOT Zynq Ultrascale-based System Board · [L1] irregular (random?) traces thickness from FPGA pads
- DIOT Zynq Ultrascale-based System Board · [L1] ESD strip3 should include also mounting hole for the front panel
- DIOT Zynq Ultrascale-based System Board · [L1] add some more GND return vias for diff pairs crossing layers
- DIOT Zynq Ultrascale-based System Board · [General] what is the estimated cost of this board today excluding the FPGA price?
- DIOT Zynq Ultrascale-based System Board · [TSilk] CERN OHL license
- DIOT Zynq Ultrascale-based System Board · [TSilk] modifications
- DIOT Zynq Ultrascale-based System Board · [General] Do we ABSOLUTELY need 0201 capacitors and resistors?
- DIOT Zynq Ultrascale-based System Board · [L14] C43 not at 45 degree angle
- DIOT Zynq Ultrascale-based System Board · [L14] Could IC24 be placed on top side of PCB?
- DIOT Zynq Ultrascale-based System Board · [L6GND] small cutouts placed around certain pins of IC1 (like SRC_CLK_SEL_R) or P2V5 vias next to C297. What are they for?
- DIOT Zynq Ultrascale-based System Board · [L5] DDR4 PAR signal (FPGA pin AH18), minor plane crossing with L4PWR.
- DIOT Zynq Ultrascale-based System Board · [General] minor impedance discontinuities - on slow LVDS improve only if possible
- DIOT Zynq Ultrascale-based System Board · [General] check DDR4 rules
- DIOT Zynq Ultrascale-based System Board · [General] Length match FMC MGTs (difference of 10 mm)
- DIOT Zynq Ultrascale-based System Board · [General] Length match FMC.CLK_M2C 0 and 1 (difference of 20 mm)
- DIOT Zynq Ultrascale-based System Board · [sch] Power IC3 from VBus instead of 3v3.
- DIOT Zynq Ultrascale-based System Board · [L1] Check via count vs current on P5VREG near C296
- DIOT Zynq Ultrascale-based System Board · [General] try to equalize via counts from high current power supplies to power planes
- DIOT Zynq Ultrascale-based System Board · [L1, L14] IC30, IC31 - add more vias on the thermal pads and expose (no soldermask) GND area on bottom layer.
- DIOT Zynq Ultrascale-based System Board · [L1, L14] IC1, IC4 - add more vias on the thermal pads and expose (no soldermask) GND area on bottom layer.
- DIOT Zynq Ultrascale-based System Board · [L1] C308/L12 and around: minor component courtyard overlaps. No real collision between components.
- DIOT Zynq Ultrascale-based System Board · [General] Clearance rule: do we really need 3 mils?
- DIOT Zynq Ultrascale-based System Board · [General] Reinforce mounting pads such as B3 with via rings.
- DIOT Zynq Ultrascale-based System Board · [General] Mounting pads for FPGA heatsink/fan
- DIOT Zynq Ultrascale-based System Board · [General] Clearance to unplated holes is a bit too tight
- DIOT Zynq Ultrascale-based System Board · [ General] Disable polygon connection (including thermals) to all BGA pads
- DIOT Zynq Ultrascale-based System Board · [General] (X:216mm Y:88.5mm) what's the purpose of that via between backplane P6 connector pins? There is GND pin right next to it.
- DIOT Zynq Ultrascale-based System Board · [General] Impedance of differential pairs not always 100 Ohm, very thin traces (0.075mm)
- DIOT Zynq Ultrascale-based System Board · [General] Clock lanes <n>_PE_CLK_P/N of backplane connector P5 (J31) shall be length matched to provide low-skew clock distribution
- DIOT Zynq Ultrascale-based System Board · slot7.lvds_0 and slot7.lvds_8 have p/n swapped comparing to FPGA pins functions
- DIOT Zynq Ultrascale-based System Board · Large vias copied from EDA-03828
- DIOT Zynq Ultrascale-based System Board · Swap FMC section with SFP section
- DIOT Zynq Ultrascale-based System Board · J6 could be closer to FPGA, it is there to power optional Zynq fan
- DIOT Zynq Ultrascale-based System Board · can we remove LD6 from the front panel and move MicroUSB (J2) to the front panel instead?
- DIOT Zynq Ultrascale-based System Board · [General] Xilinx BGA package delays