Closed
Milestone
layout-v1.0
Unstarted Issues (open and unassigned)
0
Ongoing Issues (open and assigned)
0
Completed Issues (closed)
24
- Power_Supply_2: can we add an optional pull-up on EN_P1V8_FMC?
- FPGA_Bank_44-46_48_FMC: Verify schematics note
- Silkscreen: add hyperlinks
- Remove 2 unnecessary mounting holes
- Change J9 to 2.54 mm pitch
- Add copper balancing pattern on L1 and L12
- Some return vias are missing
- Increase clearance between traces and FMC mounting holes
- Some traces are very close to FPGA heatsink mounting holes
- L12: P1V8_FMC polygon could be extended to fully cover also the last via
- L8: STRIP1 polygon accidentally cut with keep-out layer
- Consider modifying the board stack-up
- different thickness of DDR lines depending on layer?
- L3: effective width of FMC_VREFA_M2C and FMC_VREFB_M2C polygons
- L12: add thermal pads (GND) for IRPS5401 (IC21, IC22)
- Missing table with layers stackup and total board thickness
- Restore components designators
- Acid traps
- 236 DRC errors, mostly on length matching but also on front panel LEMO collision
- Backplane MGT vs LVDS lanes routing
- [FPGA_Bank_66_67_68_DDR] forbidden I/O assignment
- Consider adding pin swapping groups to the FPGA
- Remove wires from unused FPGA pins
- 0R resistors might cause short circuits