Consider modifying the board stack-up
As it stands, L4PWR doesn't have an adjacent reference plane, leaving distributed capacitance on the table.
Here's a proposed alternative:
Layer | Usage |
---|---|
Top | Signal |
L2GND | Plane |
L3 | Signal |
L5 | Signal |
L6GND | Plane |
L4PWR | Plane |
L7PWR | Plane |
L9GND | Plane |
L8 | Signal |
L10 | Signal |
L11GND | Plane |
Bottom | Signal |
As far as L4PWR is concerned, it is pushed a bit further into the stack which should slightly degrade the parasitic inductance of the vias that power the FPGA, but as indicated by the P0V95 rail PI simulation, this is totally offset by the improvement the added distributed capacitance offers: 20mΩ vs 30mΩ @100MHz.
Original stack-up
Proposed stack-up
This stack-up also carries the benefit of slightly smaller impedance discontinuities due to the (non-continuous) power planes being further away from the traces, so they're coupled tighter to the (continuous) GND planes.
The disadvantage is some crosstalk between some L3-L5 & L8-L10 traces (in an extreme case, LA30-LA32, I saw in the SI simulation a 10% near-end cross-talk, in others it's less than 5%) but this can be significantly reduced by slightly increasing dielectric thickness from 5mil to 6-7mil between L3-L5 and L8-L10.