Issues · Projects · Open Hardware Repository

Problems with clock on DUT output??

fmc-mtlu-gw#11 · opened Feb 14, 2020 by David Cussans
- 0
updated Feb 14, 2020
[fpga-bank-87-88] FPGA_WD_n near IC33 is not connected to FPGA at bank 27

diot-sb-zu#134 · opened Feb 14, 2020 by Paweł Kulik Important sch-v1
- 0
updated Feb 14, 2020
Add configurable polarity selection

fmc-mtlu-gw#10 · opened Feb 14, 2020 by David Cussans Feb 20, 2020
- 0
updated Feb 14, 2020
Fill all 8 bits of fine time stamp

fmc-mtlu-gw#9 · opened Feb 14, 2020 by David Cussans Feb 20, 2020
- 1
updated Feb 14, 2020
DDS PD RC filter must be removed.

city#16 · opened Feb 10, 2020 by Antonin Broquet
- 0
updated Feb 10, 2020
Change AD9510 VCP pin power supply assignment

city#15 · opened Feb 10, 2020 by Antonin Broquet
- 0
updated Feb 10, 2020
WR link / activity LEDs crossed

city#14 · opened Feb 10, 2020 by Antonin Broquet
- 0
updated Feb 10, 2020
"Mounted" parameter issue on DOT050V-020.0M oscillator for WR reference clock

city#13 · opened Feb 10, 2020 by Antonin Broquet
- 0
updated Feb 10, 2020
Wrong voltage level on AD9516 active low reset line

city#12 · opened Feb 10, 2020 by Antonin Broquet
- 0
updated Feb 10, 2020
Change color of FPGA reconfiguration DONE LED

city#11 · opened Feb 10, 2020 by Antonin Broquet
- 0
updated Feb 10, 2020
U6 pull-up / pull-down resistors conflict.

city#10 · opened Feb 10, 2020 by Antonin Broquet
- 0
updated Feb 10, 2020
PPS & 10MHz LVDS/LVTTL translator and output driver placement.

city#9 · opened Feb 10, 2020 by Antonin Broquet
- 0
updated Feb 10, 2020
AD9510 function pin left unconnected

city#8 · opened Feb 10, 2020 by Antonin Broquet
- 0
updated Feb 10, 2020
IC88 & IC89 have wrong DIR configuration

city#7 · opened Feb 10, 2020 by Antonin Broquet
- 0
updated Feb 10, 2020
Ethernet PHY MDIO signals are crossed

city#6 · opened Feb 10, 2020 by Antonin Broquet
- 0
updated Feb 10, 2020
I2C wrond address pins values on IC74_DO4

city#5 · opened Feb 10, 2020 by Antonin Broquet
- 0
updated Feb 10, 2020
I2C lines mismatch from PS7 MIO to level translator IC70

city#4 · opened Feb 10, 2020 by Antonin Broquet
- 0
updated Feb 10, 2020
FPGA Bank Assignment

svec7#12 · opened Feb 05, 2020 by Mikolaj Sowinski (CTI) Ready for schematic review (CTI internal) design
- 0
updated Feb 05, 2020
FMC Connectors

svec7#10 · opened Feb 05, 2020 by Mikolaj Sowinski (CTI) Ready for schematic review (CTI internal) design
- 0
updated Feb 05, 2020
Power supply 0 of 3 tasks completed

svec7#9 · opened Feb 05, 2020 by Mikolaj Sowinski (CTI) Ready for schematic review (CTI internal) design
- 1
updated Feb 12, 2020

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