Issues · Projects · Open Hardware Repository

implement OIDs in SNMP to identify node

wrpc-sw#45 · opened Oct 29, 2020 by Adam Wujek
- 0
updated Oct 29, 2020
change value of sysObjectID to reflect WRS

wr-switch-sw#221 · opened Oct 29, 2020 by Adam Wujek
- 0
updated Oct 29, 2020
Add IP-MIB to NET-SNMP

wr-switch-sw#220 · opened Oct 29, 2020 by Adam Wujek
- 0
updated Oct 29, 2020
running wrsw_rtu breaks the operation of the switch

wr-switch-sw#219 · opened Oct 28, 2020 by Maciej Lipinski v6.1 bug
- 3
updated Oct 29, 2020
Export rtu_stat and wrs_vlans output via SNMP (as subset of BRIDGE-MIB and Q-BRIDGE-MIB)

wr-switch-sw#218 · opened Oct 28, 2020 by Adam Wujek
- 0
updated Oct 29, 2020
implement radius-802.1X

wr-switch-sw#217 · opened Oct 27, 2020 by Adam Wujek
- 0
updated Oct 29, 2020
I'd add I2C/SPI I/O expander to encode with resistor net version of the board and some unique ID chip.

diot-sb-igl#33 · opened Oct 27, 2020 by Grzegorz Daniluk sch v1.0 minor
- 0
updated Oct 27, 2020
aligning net labels

diot-sb-igl#31 · opened Oct 27, 2020 by Grzegorz Daniluk sch v1.0 cosmetics
- 0
updated Oct 27, 2020
FPGA_Banks_6_7: connecting FMC clocks

diot-sb-igl#30 · opened Oct 27, 2020 by Grzegorz Daniluk sch v1.0 question
- 0
updated Oct 27, 2020
Appending wrong string to Makefile for Quartus

hdl-make#108 · opened Oct 27, 2020 by Vladislav Borchsh
- 0
updated Oct 28, 2020
FPGA_Banks_6_7: I guess we don't need the filter circuit for SERDES_0_L23_*

diot-sb-igl#29 · opened Oct 27, 2020 by Grzegorz Daniluk sch v1.0 question
- 0
updated Oct 27, 2020
FPGA_Banks_6_7: serdes Tx/Rx shall be AC-coupled

diot-sb-igl#28 · opened Oct 27, 2020 by Grzegorz Daniluk sch v1.0 critical
- 0
updated Oct 27, 2020
Translate_GPIO_to_2V5: more uniform translation circuits

diot-sb-igl#27 · opened Oct 27, 2020 by Grzegorz Daniluk sch v1.0 minor
- 0
updated Oct 27, 2020
Connect PGND to GND and the feedback networks to AGND for all TLV62130s

fmc-profinet#49 · opened Oct 26, 2020 by Christos Gentsos sch v1.0 critical
- 0
updated Oct 27, 2020
C2 capacitor voltage rating a bit marginal

fmc-profinet#48 · opened Oct 26, 2020 by Christos Gentsos sch v1.0 critical
- 0
updated Oct 27, 2020
LEDs seem a bit underpowered

fmc-profinet#46 · opened Oct 26, 2020 by Christos Gentsos sch v1.0 cosmetics
- 0
updated Oct 27, 2020
P3V3 bypass capacitors shown next to ICs that don't use P3V3

fmc-profinet#45 · opened Oct 26, 2020 by Christos Gentsos sch v1.0 cosmetics
- 0
updated Oct 27, 2020
Monitoring: ATSAMD21G18 is known to freeze in radiation, we should also have a power cycle/reset line from FPGA

diot-sb-igl#26 · opened Oct 26, 2020 by Grzegorz Daniluk sch v1.0 critical
- 0
updated Oct 26, 2020
Top_Misc: STRIP3 shall be also connected to the front panel i.e. CHASSIS net

diot-sb-igl#25 · opened Oct 26, 2020 by Grzegorz Daniluk sch v1.0 minor
- 0
updated Oct 26, 2020
P_RST and F_RST nets are active low, they need to be renamed to _N

diot#5 · opened Oct 23, 2020 by Christos Gentsos minor specifications
- 0
updated Oct 23, 2020

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