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DIOT Zynq Ultrascale-based System Board
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DIOT Zynq Ultrascale-based System Board
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#186
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Opened
Jul 02, 2020
by
Grzegorz Daniluk
@greg.d
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[L7] some clock lines near IC4 are missing GND return vias (like it's done for 7_PE_CLK_P/N)
1_PE_CLK_P/N
4_PE_CLK_P/N
5_PE_CLK_P/N
- [x] 1_PE_CLK_P/N - [x] 4_PE_CLK_P/N - [x] 5_PE_CLK_P/N
Edited
Aug 20, 2020
by
Filip Świtakowski
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