- 01 Dec, 2023 1 commit
-
-
Maciej Lipinski authored
-
- 30 Nov, 2023 4 commits
-
-
-
Maciej Lipinski authored
-
Maciej Lipinski authored
-
Maciej Lipinski authored
- Add execution of script to generate files with repo versions - Commented out 8p synthesize, uncommeted 18p synthesis - started playing with conditional sythesis (commented out)
-
- 29 Nov, 2023 5 commits
-
-
Maciej Lipinski authored
-
Maciej Lipinski authored
- change signal names to more meaningful lj_detected_o / lj_present_o to lj_ext_gm_pll_pres_o / lj_ext_gm_clk_diff_o lj_rev_id_i to lj_periph_id_i - added pull-ups to lj_periph_id_i to make sure its "111" when unused - made the selection of LJ-related peripheral more generic
-
Maciej Lipinski authored
The Low-Jitter functionality is now integrated on some versions of the main board of the WRS. As such, we need to detect the LJ functionality itself, not a board with it. Renamed from LJD to LJ for clarity.
-
Maciej Lipinski authored
- updated the pin names to reflect the true functionality - connect only the pin that is used, this is a HACK and will need to be changed in the future.
-
li hongming authored
- dac_sel allows to support AD5683R additonally to AD5662 used so far - other modificatins, mostly clean-ups * change pll_status_i to clk_ext_i * removed unused constraints
-
- 15 Nov, 2023 15 commits
-
-
Adam Wujek authored
-
Konstantinos Blantos authored
-
Konstantinos Blantos authored
-
Konstantinos Blantos authored
-
Konstantinos Blantos authored
-
Konstantinos Blantos authored
-
Konstantinos Blantos authored
-
Konstantinos Blantos authored
Update scb_top_sim.vhd. given to the unused input ljd signals, '0' value for the simulator to not complain
-
Konstantinos Blantos authored
Update scb_top_sim.vhd so as to add missing and non-used port signals in order simulator doesn't complain
-
Konstantinos Blantos authored
-
Konstantinos Blantos authored
-
Konstantinos Blantos authored
-
Konstantinos Blantos authored
-
Konstantinos Blantos authored
-
Konstantinos Blantos authored
-
- 14 Nov, 2023 1 commit
-
-
Maciej Lipinski authored
Hm proposed master See merge request !1
-
- 17 May, 2023 1 commit
-
-
Maciej Lipinski authored
-
- 20 Dec, 2021 1 commit
-
-
Grzegorz Daniluk authored
-
- 01 Jul, 2020 1 commit
-
-
li hongming authored
1. add pll_status_i clock period constraints 2. correct the TNM_NET name of rx_rec_clk_bufin.
-
- 15 May, 2020 1 commit
-
-
li hongming authored
rather than differential signal for 10M input.
-
- 14 May, 2020 1 commit
-
-
li hongming authored
There are three types of wrs: normal wrs(mark as wrs), wrs with LJD (mark as WRS-LJD), wrs with embedded lowjitter circuits(mark as WRSLJ). lj_loopback_i/o is used to distinguish wrs from WRS-LJD and WRSLJ. lj_osc_freq_i is used to distinguish WRSLJ from WRS-LJD. lj_osc_freq_i=111 means WRSLJ. lj_osc_freq_i=others means WRS-LJD. lj_osc_freq_i[2 downto 0] need to be pulled up.
-
- 06 Apr, 2020 1 commit
-
-
Grzegorz Daniluk authored
-
- 03 Apr, 2020 1 commit
-
-
Grzegorz Daniluk authored
-
- 20 Jan, 2020 1 commit
-
-
Grzegorz Daniluk authored
-
- 07 Jan, 2020 1 commit
-
-
Grzegorz Daniluk authored
-
- 17 Dec, 2019 2 commits
-
-
Grzegorz Daniluk authored
-
Grzegorz Daniluk authored
-
- 09 Dec, 2019 1 commit
-
-
Grzegorz Daniluk authored
-
- 30 Aug, 2019 2 commits
-
-
Grzegorz Daniluk authored
-
Grzegorz Daniluk authored
-