Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
W
White Rabbit Switch - Gateware
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
12
Issues
12
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
Projects
White Rabbit Switch - Gateware
Commits
af932bbd
Commit
af932bbd
authored
May 14, 2020
by
li hongming
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
change the clk_10m input source as currently WRSLJ uses single end signal
rather than differential signal for 10M input.
parent
87f02277
Hide whitespace changes
Inline
Side-by-side
Showing
4 changed files
with
20 additions
and
21 deletions
+20
-21
test_scb.xise
syn/scb_18ports/test_scb.xise
+2
-2
scb_top_bare.vhd
top/bare_top/scb_top_bare.vhd
+12
-17
wrsw_top_pkg.vhd
top/bare_top/wrsw_top_pkg.vhd
+1
-0
scb_top_synthesis.vhd
top/scb_18ports/scb_top_synthesis.vhd
+5
-2
No files found.
syn/scb_18ports/test_scb.xise
View file @
af932bbd
...
...
@@ -1251,7 +1251,7 @@
<property
xil_pn:name=
"Output File Name"
xil_pn:value=
"scb_top_synthesis"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Overwrite Compiled Libraries"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Pack I/O Registers into IOBs"
xil_pn:value=
"Yes"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Pack I/O Registers/Latches into IOBs"
xil_pn:value=
"For
Outputs Only
"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Pack I/O Registers/Latches into IOBs"
xil_pn:value=
"For
Inputs and Outputs
"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Package"
xil_pn:value=
"ff1156"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Perform Advanced Analysis"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Perform Advanced Analysis Post Trace"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
...
...
@@ -1363,7 +1363,7 @@
<property
xil_pn:name=
"Use Synchronous Set"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Use Synthesis Constraints File"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"User Access Register Value"
xil_pn:value=
"None"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"User Browsed Strategy Files"
xil_pn:value=
"
"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"User Browsed Strategy Files"
xil_pn:value=
"
/opt/Xilinx/14.7/ISE_DS/ISE/data/default.xds"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"UserID Code (8 Digit Hexadecimal)"
xil_pn:value=
"0xFFFFFFFF"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"VHDL Source Analysis Standard"
xil_pn:value=
"VHDL-93"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Value Range Check"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
...
...
top/bare_top/scb_top_bare.vhd
View file @
af932bbd
...
...
@@ -145,6 +145,7 @@ entity scb_top_bare is
ljd_clk1_en
:
out
std_logic
;
ljd_clk2_en
:
out
std_logic
;
ljd_detected_o
:
out
std_logic
;
ljd_present_o
:
out
std_logic
;
ljd_osc_freq_i
:
in
std_logic_vector
(
2
downto
0
);
-- LJD AD9516
ljd_pll_mosi_o
:
out
std_logic
;
...
...
@@ -466,6 +467,7 @@ architecture rtl of scb_top_bare is
signal
nic_rtu_rsp
:
t_rtu_response
;
signal
nic_rtu_ack
:
std_logic
;
signal
ljd_present
:
std_logic
;
signal
ljd_detected
:
std_logic
;
signal
dac_main_sync_n
:
std_logic
;
signal
dac_main_sclk
:
std_logic
;
...
...
@@ -1332,12 +1334,14 @@ begin
-------------------------------------------------------------------------------
-- WRS Low jitter daughterboard
-------------------------------------------------------------------------------
ljd_present
<=
'1'
when
((
ljd_detected
=
'1'
)
and
(
ljd_osc_freq_i
/=
"111"
))
else
'0'
;
ljd_detected_o
<=
ljd_detected
;
ljd_present_o
<=
ljd_present
;
-- Redirect DAC output if external board detetected
dac_redirection
:
process
(
ljd_
detected
,
ljd_osc_freq_i
,
dac_main_sync_n
,
dac_main_sclk
,
dac_main_data
)
dac_redirection
:
process
(
ljd_
present
,
dac_main_sync_n
,
dac_main_sclk
,
dac_main_data
)
begin
if
(
ljd_
detected
=
'0'
)
then
if
(
ljd_
present
=
'0'
)
then
dac_main_sync_n_o
<=
dac_main_sync_n
;
dac_main_sclk_o
<=
dac_main_sclk
;
dac_main_data_o
<=
dac_main_data
;
...
...
@@ -1345,21 +1349,12 @@ begin
ljd_dac_main_sclk_o
<=
'0'
;
ljd_dac_main_data_o
<=
'0'
;
else
if
(
ljd_osc_freq_i
=
"111"
)
then
dac_main_sync_n_o
<=
dac_main_sync_n
;
dac_main_sclk_o
<=
dac_main_sclk
;
dac_main_data_o
<=
dac_main_data
;
ljd_dac_main_sync_n_o
<=
'0'
;
ljd_dac_main_sclk_o
<=
'0'
;
ljd_dac_main_data_o
<=
'0'
;
else
dac_main_sync_n_o
<=
'0'
;
dac_main_sclk_o
<=
'0'
;
dac_main_data_o
<=
'0'
;
ljd_dac_main_sync_n_o
<=
dac_main_sync_n
;
ljd_dac_main_sclk_o
<=
dac_main_sclk
;
ljd_dac_main_data_o
<=
dac_main_data
;
end
if
;
dac_main_sync_n_o
<=
'0'
;
dac_main_sclk_o
<=
'0'
;
dac_main_data_o
<=
'0'
;
ljd_dac_main_sync_n_o
<=
dac_main_sync_n
;
ljd_dac_main_sclk_o
<=
dac_main_sclk
;
ljd_dac_main_data_o
<=
dac_main_data
;
end
if
;
end
process
;
...
...
top/bare_top/wrsw_top_pkg.vhd
View file @
af932bbd
...
...
@@ -370,6 +370,7 @@ package wrsw_top_pkg is
ljd_clk1_en
:
out
std_logic
;
ljd_clk2_en
:
out
std_logic
;
ljd_detected_o
:
out
std_logic
;
ljd_present_o
:
out
std_logic
;
ljd_osc_freq_i
:
in
std_logic_vector
(
2
downto
0
);
ljd_pll_mosi_o
:
out
std_logic
;
ljd_pll_miso_i
:
in
std_logic
;
...
...
top/scb_18ports/scb_top_synthesis.vhd
View file @
af932bbd
...
...
@@ -331,6 +331,7 @@ architecture Behavioral of scb_top_synthesis is
signal
ext_pll_100_locked
,
ext_pll_62_locked
:
std_logic
;
signal
clk_ext_mul_locked
:
std_logic
;
signal
ljd_detected
:
std_logic
:
=
'0'
;
signal
ljd_present
:
std_logic
:
=
'0'
;
signal
ext_clk_10MHz
,
ext_clk_10MHz_bufr
,
clk_10mhz
:
std_logic
;
signal
ljd_clk_62mhz
,
ljd_clk_62mhz_bufr
:
std_logic
;
...
...
@@ -380,6 +381,7 @@ architecture Behavioral of scb_top_synthesis is
ljd_clk1_en
:
out
std_logic
;
ljd_clk2_en
:
out
std_logic
;
ljd_detected_o
:
out
std_logic
;
ljd_present_o
:
out
std_logic
;
ljd_osc_freq_i
:
in
std_logic_vector
(
2
downto
0
);
ljd_pll_mosi_o
:
out
std_logic
;
ljd_pll_miso_i
:
in
std_logic
;
...
...
@@ -625,8 +627,8 @@ begin
O
=>
clk_10mhz
,
I0
=>
clk_ext
,
I1
=>
ext_clk_10MHz_bufr
,
S1
=>
ljd_detected
,
S0
=>
NOT
ljd_detected
);
S1
=>
ljd_present
,
S0
=>
NOT
ljd_present
);
U_Buf_CLK_DMTD
:
IBUFGDS
generic
map
(
...
...
@@ -896,6 +898,7 @@ begin
ljd_clk1_en
=>
ljd_clk1_en
,
ljd_clk2_en
=>
ljd_clk2_en
,
ljd_detected_o
=>
ljd_detected
,
ljd_present_o
=>
ljd_present
,
ljd_osc_freq_i
=>
ljd_osc_freq_i
,
ljd_pll_mosi_o
=>
ljd_pll_mosi_o
,
ljd_pll_miso_i
=>
ljd_pll_miso_i
,
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment