Commit 5d5f1a74 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

Merge branch 'greg-lpd-rebased' into proposed_master

parents 205a4500 868072d9
......@@ -5,8 +5,8 @@ modules = { "local" : [
"modules/wrsw_tru",
"modules/wrsw_tatsu",
"modules/wrsw_pstats",
"modules/wrsw_hwiu",
"modules/wrsw_watchdog",
"modules/wrsw_hwiu",
"modules/wrsw_watchdog",
"platform/virtex6/chipscope",
"platform/xilinx",
"ip_cores/wr-cores",
......
Subproject commit 17d08e592c482848bf1ce9401f39a2a8749d04f4
Subproject commit dcc7cc33ffa3bce1a9a3da9ea317e3c768830398
Subproject commit b23b87769f895a8f75402ac47b401bf02bff6a57
Subproject commit 25deb51759cf467df4fdeeca3bd10e4e793f71ca
......@@ -39,6 +39,9 @@ package wrsw_shared_types_pkg is
constant c_RTU_MAX_PORTS : integer := 32;
constant c_SWC_MAX_PORTS : integer := c_RTU_MAX_PORTS+1;
type t_bool_array is array(integer range <>) of boolean;
constant c_BOOL_FALSE_ARRAY : t_bool_array(0 to 17) := (others=>false);
type t_rtu_request is record
valid : std_logic;
smac : std_logic_vector(47 downto 0);
......
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Created : 2012-02-21
-- Last update: 2014-03-17
-- Last update: 2018-11-07
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -64,7 +64,8 @@ entity scb_top_bare is
g_with_PSTATS : boolean := true;
g_with_muxed_CS : boolean := false;
g_with_watchdog : boolean := false;
g_inj_per_EP : std_logic_vector(17 downto 0) := (others=>'0')
g_inj_per_EP : std_logic_vector(17 downto 0) := (others=>'0');
g_phy_lpcalib : t_bool_array(0 to 17) := c_BOOL_FALSE_ARRAY
);
port (
sys_rst_n_i : in std_logic; -- global reset
......@@ -282,7 +283,7 @@ architecture rtl of scb_top_bare is
-------------------------------------------------------------------------------
signal clk_sys : std_logic;
signal clk_rx_vec : std_logic_vector(c_NUM_PORTS-1 downto 0);
signal clk_rx_vec, clk_rx_sampled_vec : std_logic_vector(c_NUM_PORTS-1 downto 0);
-------------------------------------------------------------------------------
......@@ -336,6 +337,7 @@ architecture rtl of scb_top_bare is
signal rst_periph_ref_n : std_logic;
signal rst_periph_dmtd_n : std_logic;
signal rst_periph_rxclk_n: std_logic_vector(c_NUM_PORTS-1 downto 0);
signal rst_periph_txclk_n: std_logic_vector(c_NUM_PORTS-1 downto 0);
signal rst_ref_n : std_logic;
signal rst_ext_n : std_logic;
signal rst_dmtd_n : std_logic;
......@@ -574,6 +576,15 @@ begin
synced_o => rst_periph_dmtd_n);
gen_rst_periph_rxclk : for i in 0 to c_NUM_PORTS-1 generate
U_sync_reset_txclk : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => phys_i(i).ref_clk,
rst_n_i => '1',
data_i => rst_n_periph,
synced_o => rst_periph_txclk_n(i));
U_sync_reset_rxclk: gc_sync_ffs
generic map (
g_sync_edge => "positive")
......@@ -603,12 +614,14 @@ begin
generic map (
g_num_rx_clocks => c_NUM_PORTS,
g_num_ext_clks => 2,
g_simulation => g_simulation)
g_simulation => g_simulation,
g_phy_lpcalib => g_phy_lpcalib)
port map (
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys,
clk_dmtd_i => clk_dmtd_i,
clk_rx_i => clk_rx_vec,
clk_rx_sampled_i => clk_rx_sampled_vec,
clk_ext_i => pll_status_i, -- FIXME: UGLY HACK
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_mul_locked_i => clk_ext_mul_locked_i,
......@@ -781,7 +794,8 @@ begin
g_use_new_rxcrc => true,
g_use_new_txcrc => false,
g_with_stop_traffic => g_with_watchdog,
g_ep_idx => i)
g_phy_lpcalib => g_phy_lpcalib(i),
g_ep_idx => i)
port map (
clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys,
......@@ -790,7 +804,7 @@ begin
rst_sys_n_i => rst_n_periph,
rst_ref_n_i => rst_periph_ref_n,
rst_dmtd_n_i => rst_periph_dmtd_n,
rst_txclk_n_i => rst_periph_ref_n,
rst_txclk_n_i => rst_periph_txclk_n(i),
rst_rxclk_n_i => rst_periph_rxclk_n(i),
pps_csync_p1_i => pps_csync,
......@@ -798,6 +812,8 @@ begin
phy_rst_o => phys_o(i).rst,
phy_loopen_o => phys_o(i).loopen,
phy_lpc_stat_i => phys_i(i).lpc_stat,
phy_lpc_ctrl_o => phys_o(i).lpc_ctrl,
phy_rdy_i => phys_i(i).rdy,
phy_ref_clk_i => phys_i(i).ref_clk,
phy_tx_data_o => ep_dbg_data_array(i), -- phys_o(i).tx_data, --
......@@ -877,6 +893,7 @@ begin
---------------------------
clk_rx_vec(i) <= phys_i(i).rx_clk;
clk_rx_sampled_vec(i) <= phys_i(i).rx_sampled_clk;
end generate gen_endpoints_and_phys;
......
......@@ -118,7 +118,8 @@ package wrsw_components_pkg is
component wr_gtx_phy_virtex6
generic (
g_simulation : integer;
g_use_slave_tx_clock : integer);
g_use_slave_tx_clock : integer;
g_rxclk_bufr : boolean);
port (
clk_ref_i : in std_logic;
tx_clk_i : in std_logic;
......
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Created : 2012-02-21
-- Last update: 2014-02-14
-- Last update: 2018-11-07
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -51,6 +51,8 @@ package wrsw_top_pkg is
syncen : std_logic;
tx_data : std_logic_vector(15 downto 0);
tx_k : std_logic_vector(1 downto 0);
lpc_ctrl: std_logic_vector(15 downto 0);
end record;
type t_phyif_input is record
......@@ -59,10 +61,12 @@ package wrsw_top_pkg is
tx_enc_err : std_logic;
rx_data : std_logic_vector(15 downto 0);
rx_clk : std_logic;
rx_sampled_clk : std_logic;
rx_k : std_logic_vector(1 downto 0);
rx_enc_err : std_logic;
rx_bitslide : std_logic_vector(4 downto 0);
rdy : std_logic;
lpc_stat : std_logic_vector(15 downto 0);
end record;
type t_phyif_output_array is array(integer range <>) of t_phyif_output;
......@@ -141,6 +145,40 @@ package wrsw_top_pkg is
rdy_o : out std_logic);
end component;
component wr_gtx_phy_virtex6_lp
generic (
g_simulation : integer;
g_use_slave_tx_clock : integer;
g_rxclk_bufr : boolean := false;
g_txclk_bufr : boolean := false;
g_id : integer);
port (
clk_ref_i : in std_logic;
clk_gtx_i : in std_logic;
clk_dmtd_i : in std_logic;
tx_data_i : in std_logic_vector(15 downto 0);
tx_k_i : in std_logic_vector(1 downto 0);
tx_disparity_o : out std_logic;
tx_enc_err_o : out std_logic;
rx_rbclk_o : out std_logic;
rx_rbclk_sampled_o : out std_logic;
rx_data_o : out std_logic_vector(15 downto 0);
rx_k_o : out std_logic_vector(1 downto 0);
rx_enc_err_o : out std_logic;
rx_bitslide_o : out std_logic_vector(4 downto 0);
rst_i : in std_logic;
loopen_i : in std_logic;
debug_i : in std_logic_vector(15 downto 0);
debug_o : out std_logic_vector(15 downto 0);
pad_txn_o : out std_logic;
pad_txp_o : out std_logic;
pad_rxn_i : in std_logic := '0';
pad_rxp_i : in std_logic := '0';
rdy_o : out std_logic
);
end component;
component xwr_pps_gen
generic (
g_interface_mode : t_wishbone_interface_mode;
......@@ -208,12 +246,15 @@ package wrsw_top_pkg is
generic (
g_num_rx_clocks : integer;
g_num_ext_clks : integer;
g_simulation : boolean);
g_simulation : boolean;
g_phy_lpcalib : t_bool_array(0 to 17));
port (
clk_ref_i : in std_logic;
clk_sys_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_rx_i : in std_logic_vector(g_num_rx_clocks-1 downto 0);
clk_rx_sampled_i : in std_logic_vector(g_num_rx_clocks-1 downto 0);
clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic_vector(g_num_ext_clks-1 downto 0);
clk_ext_mul_locked_i: in std_logic;
......@@ -299,7 +340,8 @@ package wrsw_top_pkg is
g_with_PSTATS : boolean := true;
g_with_muxed_CS : boolean := false;
g_with_watchdog : boolean := false;
g_inj_per_EP : std_logic_vector(17 downto 0) := (others=>'0'));
g_inj_per_EP : std_logic_vector(17 downto 0) := (others=>'0');
g_phy_lpcalib : t_bool_array(0 to 17) := c_BOOL_FALSE_ARRAY);
port (
sys_rst_n_i : in std_logic;
clk_startup_i : in std_logic;
......@@ -428,7 +470,8 @@ package wrsw_top_pkg is
rtu2tru_o : out t_rtu2tru;
tru_enabled_i: in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out);
wb_o : out t_wishbone_slave_out;
int_o : out std_logic);
end component;
component xwrsw_rtu_new
generic (
......
This diff is collapsed.
......@@ -44,6 +44,7 @@ use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.wr_txtsu_pkg.all;
use work.wrsw_top_pkg.all;
use work.wrsw_shared_types_pkg.all;
library UNISIM;
......@@ -345,7 +346,8 @@ architecture Behavioral of scb_top_synthesis is
g_with_PSTATS : boolean;
g_with_muxed_CS : boolean;
g_with_watchdog : boolean;
g_inj_per_EP : std_logic_vector(17 downto 0));
g_inj_per_EP : std_logic_vector(17 downto 0);
g_phy_lpcalib : t_bool_array(0 to 17) := c_BOOL_FALSE_ARRAY);
port (
sys_rst_n_i : in std_logic;
clk_startup_i : in std_logic;
......@@ -437,6 +439,57 @@ architecture Behavioral of scb_top_synthesis is
signal TRIG1 : std_logic_vector(31 downto 0);
signal TRIG2 : std_logic_vector(31 downto 0);
signal TRIG3 : std_logic_vector(31 downto 0);
type t_phy_conf is record
rxclk_bufr : boolean;
txclk_bufr : boolean;
end record;
type t_phy_conf_array is array(integer range <>) of t_phy_conf;
constant c_PHY_CONF : t_phy_conf_array(0 to 17) :=
( -- rx_bufr, tx_bufr
0 => (false , true ),
1 => (false , true ),
2 => (false , true ),
3 => (false , true ),
4 => (false , false ),
5 => (false , false ),
6 => (false , false ),
7 => (false , false ),
8 => (false , true ),
9 => (false , true ),
10 => (false , true ),
11 => (false , true ),
12 => (false , false ),
13 => (false , false ),
14 => (false , false ),
15 => (false , false ),
16 => (true , false ),
17 => (true , false )
);
constant c_PHY_LPCALIB : t_bool_array(0 to 17) :=
(
0 => true,
1 => true,
2 => true,
3 => true,
4 => true,
5 => true,
6 => true,
7 => true,
8 => true,
9 => true,
10 => true,
11 => true,
12 => false,
13 => false,
14 => false,
15 => false,
16 => false,
17 => false
);
begin
--chipscope_icon_1 : chipscope_icon
......@@ -713,65 +766,72 @@ begin
clk_gtx(13 downto 10) <= (others => clk_gtx4_7);
clk_gtx(17 downto 14) <= (others => clk_gtx0_3);
--generate first 4 GTXes with BUFR to reduce the number of global clocks
gen_phys_bufr : for i in 0 to 3 generate
U_PHY : wr_gtx_phy_virtex6
generic map (
g_simulation => f_bool2int(g_simulation),
g_use_slave_tx_clock => f_bool2int(i /= (i/4)*4),
g_use_bufr => true)
port map (
clk_gtx_i => clk_gtx(i),
clk_ref_i => clk_ref,
tx_data_i => to_phys(i).tx_data,
tx_k_i => to_phys(i).tx_k,
tx_disparity_o => from_phys(i).tx_disparity,
tx_enc_err_o => from_phys(i).tx_enc_err,
rx_rbclk_o => from_phys(i).rx_clk,
rx_data_o => from_phys(i).rx_data,
rx_k_o => from_phys(i).rx_k,
rx_enc_err_o => from_phys(i).rx_enc_err,
rx_bitslide_o => from_phys(i).rx_bitslide,
rst_i => to_phys(i).rst,
loopen_i => to_phys(i).loopen,
pad_txn_o => gtx_txn_o(i),
pad_txp_o => gtx_txp_o(i),
pad_rxn_i => gtx_rxn_i(i),
pad_rxp_i => gtx_rxp_i(i),
rdy_o => from_phys(i).rdy);
from_phys(i).ref_clk <= clk_ref;
end generate gen_phys_bufr;
gen_phys : for i in 4 to c_NUM_PHYS-1 generate
U_PHY : wr_gtx_phy_virtex6
generic map (
g_simulation => f_bool2int(g_simulation),
g_use_slave_tx_clock => f_bool2int(i /= (i/4)*4),
g_use_bufr => false)
port map (
clk_gtx_i => clk_gtx(i),
clk_ref_i => clk_ref,
tx_data_i => to_phys(i).tx_data,
tx_k_i => to_phys(i).tx_k,
tx_disparity_o => from_phys(i).tx_disparity,
tx_enc_err_o => from_phys(i).tx_enc_err,
rx_rbclk_o => from_phys(i).rx_clk,
rx_data_o => from_phys(i).rx_data,
rx_k_o => from_phys(i).rx_k,
rx_enc_err_o => from_phys(i).rx_enc_err,
rx_bitslide_o => from_phys(i).rx_bitslide,
rst_i => to_phys(i).rst,
loopen_i => to_phys(i).loopen,
pad_txn_o => gtx_txn_o(i),
pad_txp_o => gtx_txp_o(i),
pad_rxn_i => gtx_rxn_i(i),
pad_rxp_i => gtx_rxp_i(i),
rdy_o => from_phys(i).rdy);
gen_phys : for i in 0 to c_NUM_PHYS-1 generate
-- Instantiate GTX with low phase drift calibration
gen_lp: if c_PHY_LPCALIB(i) generate
U_PHY : entity work.wr_gtx_phy_virtex6_lp
generic map (
g_simulation => f_bool2int(g_simulation),
g_rxclk_bufr => c_PHY_CONF(i).rxclk_bufr,
g_txclk_bufr => c_PHY_CONF(i).txclk_bufr,
g_id => i)
port map (
clk_gtx_i => clk_gtx(i),
clk_ref_i => clk_ref,
clk_dmtd_i => clk_dmtd,
tx_data_i => to_phys(i).tx_data,
tx_k_i => to_phys(i).tx_k,
tx_disparity_o => from_phys(i).tx_disparity,
tx_enc_err_o => from_phys(i).tx_enc_err,
rx_rbclk_o => from_phys(i).rx_clk,
clk_sampled_o => from_phys(i).rx_sampled_clk,
rx_data_o => from_phys(i).rx_data,
rx_k_o => from_phys(i).rx_k,
rx_enc_err_o => from_phys(i).rx_enc_err,
rx_bitslide_o => from_phys(i).rx_bitslide,
rst_i => to_phys(i).rst,
lpc_stat_o => from_phys(i).lpc_stat,
lpc_ctrl_i => to_phys(i).lpc_ctrl,
loopen_i => to_phys(i).loopen,
pad_txn_o => gtx_txn_o(i),
pad_txp_o => gtx_txp_o(i),
pad_rxn_i => gtx_rxn_i(i),
pad_rxp_i => gtx_rxp_i(i),
rdy_o => from_phys(i).rdy);
end generate gen_lp;
-- Instantiate regular GTX for all other ports
gen_no_lp: if not c_PHY_LPCALIB(i) generate
U_PHY : entity work.wr_gtx_phy_virtex6
generic map (
g_simulation => f_bool2int(g_simulation),
g_rxclk_bufr => c_PHY_CONF(i).rxclk_bufr)
port map (
clk_gtx_i => clk_gtx(i),
clk_ref_i => clk_ref,
tx_data_i => to_phys(i).tx_data,
tx_k_i => to_phys(i).tx_k,
tx_disparity_o => from_phys(i).tx_disparity,
tx_enc_err_o => from_phys(i).tx_enc_err,
rx_rbclk_o => from_phys(i).rx_clk,
rx_data_o => from_phys(i).rx_data,
rx_k_o => from_phys(i).rx_k,
rx_enc_err_o => from_phys(i).rx_enc_err,
rx_bitslide_o => from_phys(i).rx_bitslide,
rst_i => to_phys(i).rst,
loopen_i => to_phys(i).loopen,
pad_txn_o => gtx_txn_o(i),
pad_txp_o => gtx_txp_o(i),
pad_rxn_i => gtx_rxn_i(i),
pad_rxp_i => gtx_rxp_i(i),
rdy_o => from_phys(i).rdy);
from_phys(i).rx_sampled_clk <= '0';
from_phys(i).lpc_stat <= (others => '0');
end generate gen_no_lp;
from_phys(i).ref_clk <= clk_ref;
end generate gen_phys;
......@@ -801,7 +861,8 @@ begin
g_with_PSTATS => true,
g_with_muxed_CS => false,
g_with_watchdog => true,
g_inj_per_EP => "00" & x"0000")
g_inj_per_EP => "00" & x"0000",
g_phy_lpcalib => c_PHY_LPCALIB)
port map (
sys_rst_n_i => sys_rst_n_i,
clk_startup_i => clk_sys_startup,
......
This diff is collapsed.
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Created : 2012-03-07
-- Last update: 2014-03-20
-- Last update: 2019-07-03
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -44,7 +44,7 @@ use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.wr_txtsu_pkg.all;
use work.wrsw_top_pkg.all;
use work.wrsw_shared_types_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
......@@ -345,7 +345,8 @@ architecture Behavioral of scb_top_synthesis is
g_with_PSTATS : boolean;
g_with_muxed_CS : boolean;
g_with_watchdog : boolean;
g_inj_per_EP : std_logic_vector(17 downto 0));
g_inj_per_EP : std_logic_vector(17 downto 0);
g_phy_lpcalib : t_bool_array(0 to 17) := c_BOOL_FALSE_ARRAY);
port (
sys_rst_n_i : in std_logic;
clk_startup_i : in std_logic;
......@@ -437,51 +438,39 @@ architecture Behavioral of scb_top_synthesis is
signal TRIG1 : std_logic_vector(31 downto 0);
signal TRIG2 : std_logic_vector(31 downto 0);
signal TRIG3 : std_logic_vector(31 downto 0);
begin
--chipscope_icon_1 : chipscope_icon
-- port map (
-- CONTROL0 => CONTROL);
--chipscope_ila_1 : chipscope_ila
-- port map (
-- CONTROL => CONTROL,
-- CLK => clk_25mhz,
-- TRIG0 => TRIG0,
-- TRIG1 => TRIG1,
-- TRIG2 => TRIG2,
-- TRIG3 => TRIG3);
--TRIG0(0) <= mbl_scl_b(0);
--TRIG0(1) <= mbl_sda_b(0);
--TRIG0(2) <= mbl_scl_b(1);
--TRIG0(3) <= mbl_sda_b(1);
--TRIG1 <= cpu_data_b;
--TRIG2(0) <= cpu_cs_n_i;
--TRIG2(1) <= cpu_rd_n_i;
--TRIG2(2) <= cpu_wr_n_i;
--TRIG2(3) <= sys_rst_n_i;
--U_Clk_Buf_GTX0_3 : IBUFDS_GTXE1
-- port map
-- (
-- O => clk_gtx0_3,
-- ODIV2 => open,
-- CEB => '0',
-- I => gtx0_3_clk_p_i,
-- IB => gtx0_3_clk_n_i
-- );
--U_Clk_Buf_GTX4_7 : IBUFDS_GTXE1
-- port map
-- (
-- O => clk_gtx4_7,
-- ODIV2 => open,
-- CEB => '0',
-- I => gtx4_7_clk_p_i,
-- IB => gtx4_7_clk_n_i
-- );
type t_phy_conf is record
rxclk_bufr : boolean;
txclk_bufr : boolean;
end record;
type t_phy_conf_array is array(integer range <>) of t_phy_conf;
constant c_PHY_CONF : t_phy_conf_array(0 to 7) :=
( -- rx_bufr, tx_bufr
0 => (false , true ),
1 => (false , true ),
2 => (false , true ),
3 => (false , true ),
4 => (false , false ),
5 => (false , false ),
6 => (false , false ),
7 => (false , false )
);
constant c_PHY_LPCALIB : t_bool_array(0 to 17) :=
(
0 => true,
1 => true,
2 => true,
3 => true,
4 => true,
5 => true,
6 => true,
7 => true,
others => false
);
begin
U_Clk_Buf_GTX8_11 : IBUFDS_GTXE1
port map
......@@ -646,15 +635,15 @@ begin
clk_ext_mul_vec(1) <= ljd_clk_62mhz_bufr;
--dbg_clk_ext_o <= clk_ext_mul;
local_reset <= not sys_rst_n_i;
U_Extend_EXT_Reset: gc_extend_pulse
generic map (
g_width => 1000)
port map(
clk_i => clk_sys,
rst_n_i => sys_rst_n_i,
pulse_i => local_reset,
extended_o => ext_pll_reset);
local_reset <= not sys_rst_n_i;
U_Extend_EXT_Reset: gc_extend_pulse
generic map (
g_width => 1000)
port map(
clk_i => clk_sys,
rst_n_i => sys_rst_n_i,
pulse_i => local_reset,
extended_o => ext_pll_reset);
------------------------------------------------
cmp_wb_cpu_bridge : wb_cpu_bridge
......@@ -716,64 +705,70 @@ begin
--clk_gtx(14 downto 12) <= (others => clk_gtx12_15);
--clk_gtx(17 downto 16) <= (others => clk_gtx16_19);
--generate first 4 GTXes with BUFR to reduce the number of global clocks
gen_phys_bufr : for i in 0 to 3 generate
U_PHY : wr_gtx_phy_virtex6
generic map (
g_simulation => f_bool2int(g_simulation),
g_use_slave_tx_clock => f_bool2int(i /= (i/4)*4),
g_use_bufr => true)
port map (
clk_gtx_i => clk_gtx(i),
clk_ref_i => clk_ref,
tx_data_i => to_phys(i).tx_data,
tx_k_i => to_phys(i).tx_k,
tx_disparity_o => from_phys(i).tx_disparity,
tx_enc_err_o => from_phys(i).tx_enc_err,
rx_rbclk_o => from_phys(i).rx_clk,
rx_data_o => from_phys(i).rx_data,
rx_k_o => from_phys(i).rx_k,
rx_enc_err_o => from_phys(i).rx_enc_err,
rx_bitslide_o => from_phys(i).rx_bitslide,
rst_i => to_phys(i).rst,
loopen_i => to_phys(i).loopen,
pad_txn_o => gtx_txn_o(i),
pad_txp_o => gtx_txp_o(i),
pad_rxn_i => gtx_rxn_i(i),
pad_rxp_i => gtx_rxp_i(i),
rdy_o => from_phys(i).rdy);
from_phys(i).ref_clk <= clk_ref;
end generate gen_phys_bufr;
gen_phys : for i in 4 to c_NUM_PHYS-1 generate
U_PHY : wr_gtx_phy_virtex6
generic map (
g_simulation => f_bool2int(g_simulation),
g_use_slave_tx_clock => f_bool2int(i /= (i/4)*4),
g_use_bufr => false)
port map (
clk_gtx_i => clk_gtx(i),
clk_ref_i => clk_ref,
tx_data_i => to_phys(i).tx_data,
tx_k_i => to_phys(i).tx_k,
tx_disparity_o => from_phys(i).tx_disparity,
tx_enc_err_o => from_phys(i).tx_enc_err,
rx_rbclk_o => from_phys(i).rx_clk,
rx_data_o => from_phys(i).rx_data,
rx_k_o => from_phys(i).rx_k,
rx_enc_err_o => from_phys(i).rx_enc_err,
rx_bitslide_o => from_phys(i).rx_bitslide,
rst_i => to_phys(i).rst,
loopen_i => to_phys(i).loopen,
pad_txn_o => gtx_txn_o(i),
pad_txp_o => gtx_txp_o(i),
pad_rxn_i => gtx_rxn_i(i),
pad_rxp_i => gtx_rxp_i(i),
rdy_o => from_phys(i).rdy);
gen_phys : for i in 0 to c_NUM_PHYS-1 generate
-- Instantiate GTX with low phase drift calibration
gen_lp: if c_PHY_LPCALIB(i) generate
U_PHY : entity work.wr_gtx_phy_virtex6_lp
generic map (
g_simulation => f_bool2int(g_simulation),
g_rxclk_bufr => c_PHY_CONF(i).rxclk_bufr,
g_txclk_bufr => c_PHY_CONF(i).txclk_bufr,
g_id => i)
port map (
clk_gtx_i => clk_gtx(i),
clk_ref_i => clk_ref,
clk_dmtd_i => clk_dmtd,
tx_data_i => to_phys(i).tx_data,
tx_k_i => to_phys(i).tx_k,
tx_disparity_o => from_phys(i).tx_disparity,
tx_enc_err_o => from_phys(i).tx_enc_err,
rx_rbclk_o => from_phys(i).rx_clk,
clk_sampled_o =>from_phys(i).rx_sampled_clk,
rx_data_o => from_phys(i).rx_data,
rx_k_o => from_phys(i).rx_k,
rx_enc_err_o => from_phys(i).rx_enc_err,
rx_bitslide_o => from_phys(i).rx_bitslide,
rst_i => to_phys(i).rst,
lpc_stat_o => from_phys(i).lpc_stat,
lpc_ctrl_i => to_phys(i).lpc_ctrl,
loopen_i => to_phys(i).loopen,
pad_txn_o => gtx_txn_o(i),
pad_txp_o => gtx_txp_o(i),
pad_rxn_i => gtx_rxn_i(i),
pad_rxp_i => gtx_rxp_i(i),
rdy_o => from_phys(i).rdy);
end generate gen_lp;
-- Instantiate regular GTX for all other ports
gen_no_lp: if not c_PHY_LPCALIB(i) generate
U_PHY : entity work.wr_gtx_phy_virtex6
generic map (
g_simulation => f_bool2int(g_simulation),
g_rxclk_bufr => c_PHY_CONF(i).rxclk_bufr)
port map (