pstats: add registers to improve timing

982b8362 · Grzegorz Daniluk · 3cc77ba7 · 982b8362
Commit 982b8362 authored Dec 17, 2019 by Grzegorz Daniluk
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port_cntr.vhd modules/wrsw_pstats/port_cntr.vhd +9 -1

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--- a/modules/wrsw_pstats/port_cntr.vhd
+++ b/modules/wrsw_pstats/port_cntr.vhd
@@ -167,7 +167,15 @@ begin


  GEN_EVT_ORED : for i in 0 to c_rr_range-1 generate
-    events_ored(i) <= or_reduce(events_reg((i+1)*g_cnt_pw-1 downto i*g_cnt_pw));
+    process(clk_i)
+    begin
+      if rst_n_i = '0' then
+        events_ored(i) <= '0';
+      elsif rising_edge(clk_i) then
+        events_ored(i) <= or_reduce(events_reg((i+1)*g_cnt_pw-1 downto
+                          i*g_cnt_pw)) and (not events_grant(i));
+      end if;
+    end process;
  end generate;

  events_presub <= events_reg((f_onehot_decode(events_grant)+1)*g_cnt_pw-1 downto f_onehot_decode(events_grant)*g_cnt_pw);