Commit b11b0cc6 authored by Maciej Lipinski's avatar Maciej Lipinski

8P: fixed 8 ports top, some fix to sim as well

parent d9b3cc2a
Pipeline #5003 passed with stage
in 107 minutes and 25 seconds
......@@ -227,7 +227,7 @@ begin -- rtl
i2c_sda_o => i2c_sda_out,
i2c_sda_i => i2c_sda_in,
lj_loopback_i => '0',
lj_osc_freq_i => (others=>'0'),
lj_osc_freq_i => (others=>'1'),
lj_pll_miso_i => '0',
lj_pll_locked_i=> '0'
);
......
......@@ -25,12 +25,12 @@ INST "BUFGMUX_inst" LOC = BUFGCTRL_X0Y1;
NET "lj_clk_62mhz_p_i" LOC = AN33;
NET "lj_clk_62mhz_n_i" LOC = AN34;
NET "lj_rev_id_i[0]" LOC = AE29;
NET "lj_rev_id_i[0]" PULLUP;
NET "lj_rev_id_i[1]" LOC = AE28;
NET "lj_rev_id_i[1]" PULLUP;
NET "lj_rev_id_i[2]" LOC = AM32;
NET "lj_rev_id_i[2]" PULLUP;
NET "lj_periph_id_i[0]" LOC = AE29;
NET "lj_periph_id_i[0]" PULLUP;
NET "lj_periph_id_i[1]" LOC = AE28;
NET "lj_periph_id_i[1]" PULLUP;
NET "lj_periph_id_i[2]" LOC = AM32;
NET "lj_periph_id_i[2]" PULLUP;
NET "lj_osc_freq_i[0]" LOC = AN32;
NET "lj_osc_freq_i[0]" PULLUP;
......@@ -133,6 +133,11 @@ NET "dac_main_sync_n_o" LOC="AM17";
NET "dac_main_sclk_o" LOC="AN17";
NET "dac_main_data_o" LOC="AP17";
NET "wd_scl_i" LOC="T24";
NET "wd_sda_b" LOC="T23";
NET "wd_int_i" LOC="AC23";
NET "wd_int_i" PULLUP;# just in case it is not connected in future designs
NET "lj_dac_main_sync_n_o" LOC = AH32;
NET "lj_dac_main_sclk_o" LOC = AK32;
NET "lj_dac_main_data_o" LOC = AK33;
......@@ -385,6 +390,9 @@ AREA_GROUP "pblock_ext_dmtd_2" PLACE=CLOSED;
TIMESPEC ts_ignore_xclk1 = FROM "fpga_clk_ref_p_i" TO "U_swcore_pll_clkout0" 20 ns DATAPATHONLY;
TIMESPEC ts_ignore_xclk2 = FROM "U_swcore_pll_clkout0" TO "fpga_clk_ref_p_i" 20 ns DATAPATHONLY;
NET "clk_ext_i" TNM_NET = "fpga_clk_10mhz_i";
TIMESPEC TS_fpga_clk_10mhz_i = PERIOD "fpga_clk_10mhz_i" 100 ns HIGH 50 %;
#Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2019/07/12
NET "gen_phys[0].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[0].gen_lp.U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_0__gen_lp_U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[0].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
......
......@@ -71,6 +71,9 @@ entity scb_top_synthesis is
fpga_clk_dmtd_n_i : in std_logic;
-- External 10MHz input
clk_ext_i : in std_logic;
-- 10MHz out clock generated from oserdes
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
......@@ -151,7 +154,7 @@ entity scb_top_synthesis is
lj_clk1_en : out std_logic;
lj_clk2_en : out std_logic;
lj_osc_freq_i : in std_logic_vector (2 downto 0);
lj_rev_id_i : in std_logic_vector (2 downto 0);
lj_periph_id_i: in std_logic_vector (2 downto 0);
uart_txd_o : out std_logic;
......@@ -337,7 +340,18 @@ architecture Behavioral of scb_top_synthesis is
signal ext_pll_100_locked, ext_pll_62_locked : std_logic;
signal clk_ext_mul_locked : std_logic;
signal lj_detected : std_logic := '0';
-- when lj_ext_gm_pll_pres = '0':
-- FPGA-internal PLL is used to multiply input clock from 10MHz to 62.5MHz
-- when lj_ext_gm_pll_pres = '1':
-- external PLL is present and used to multiply input clock from 10MHz to 62.5MHz
signal lj_ext_gm_pll_pres : std_logic := '0';
-- when lj_ext_gm_clk_diff = '0'
-- single-ended 10 MHz input clock at pin K13 is used as input for 10MHz signal to SoftPLL
-- when lj_ext_gm_clk_diff = '1'
-- differencial 10 MHz input clock at pin AF30/AG30 is used as input for 10MHz signal to SoftPLL
signal lj_ext_gm_clk_diff : std_logic := '0';
signal ext_clk_10MHz, ext_clk_10MHz_bufr, clk_10mhz : std_logic;
signal lj_clk_62mhz, lj_clk_62mhz_bufr : std_logic;
......@@ -360,6 +374,7 @@ architecture Behavioral of scb_top_synthesis is
clk_ref_i : in std_logic;
clk_dmtd_i : in std_logic;
clk_aux_i : in std_logic;
clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic_vector(1 downto 0);
clk_ext_mul_locked_i: in std_logic;
clk_aux_p_o : out std_logic;
......@@ -385,8 +400,10 @@ architecture Behavioral of scb_top_synthesis is
lj_loopback_o : out std_logic;
lj_clk1_en : out std_logic;
lj_clk2_en : out std_logic;
lj_detected_o : out std_logic;
lj_osc_freq_i : in std_logic_vector (2 downto 0);
lj_ext_gm_pll_pres_o : out std_logic;
lj_ext_gm_clk_diff_o : out std_logic;
lj_osc_freq_i : in std_logic_vector (2 downto 0) := (others=>'1');
lj_periph_id_i : in std_logic_vector (2 downto 0) := (others=>'1');
lj_pll_mosi_o : out std_logic;
lj_pll_miso_i : in std_logic;
lj_pll_sck_o : out std_logic;
......@@ -394,7 +411,6 @@ architecture Behavioral of scb_top_synthesis is
lj_pll_sync_n_o : out std_logic;
lj_pll_reset_n_o : out std_logic;
lj_pll_locked_i : in std_logic;
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
......@@ -406,6 +422,9 @@ architecture Behavioral of scb_top_synthesis is
clk_en_o : out std_logic;
clk_sel_o : out std_logic;
uart_sel_o : out std_logic;
wd_int_i : in std_logic := '1';
wd_scl_i : in std_logic := '1';
wd_sda_b : inout std_logic;
clk_dmtd_divsel_o : out std_logic;
phys_o : out t_phyif_output_array(g_num_ports-1 downto 0);
phys_i : in t_phyif_input_array(g_num_ports-1 downto 0);
......@@ -419,12 +438,12 @@ architecture Behavioral of scb_top_synthesis is
i2c_sda_oen_o : out std_logic_vector(2 downto 0);
i2c_sda_o : out std_logic_vector(2 downto 0);
i2c_sda_i : in std_logic_vector(2 downto 0) := "111";
mb_fan1_pwm_o : out std_logic;
mb_fan2_pwm_o : out std_logic;
mb_fan1_pwm_o : out std_logic;
mb_fan2_pwm_o : out std_logic;
spll_dbg_o : out std_logic_vector(5 downto 0)
);
end component;
component chipscope_icon
port (
CONTROL0 : inout std_logic_vector(35 downto 0));
......@@ -568,8 +587,8 @@ begin
O => clk_10mhz,
I0 => clk_ext,
I1 => ext_clk_10MHz_bufr,
S1 => lj_detected,
S0 => NOT lj_detected
S1 => lj_ext_gm_clk_diff,
S0 => NOT lj_ext_gm_clk_diff
);
U_Buf_CLK_DMTD : IBUFGDS
......@@ -626,7 +645,7 @@ begin
clk_ext_i => clk_ext,
clk_ext_100_o => clk_ext_100,
rst_a_i => ext_pll_reset,
powerdown_i => lj_detected,
powerdown_i => lj_ext_gm_pll_pres,
locked_o => ext_pll_100_locked);
U_Ext_PLL2: ext_pll_100_to_62m
......@@ -634,7 +653,7 @@ begin
clk_ext_100_i => clk_ext_100,
clk_ext_mul_o => clk_ext_mul,
rst_a_i => ext_pll_reset,
powerdown_i => lj_detected,
powerdown_i => lj_ext_gm_pll_pres,
locked_o => ext_pll_62_locked);
clk_ext_mul_locked <= ext_pll_100_locked and ext_pll_62_locked;
......@@ -814,6 +833,7 @@ begin
clk_dmtd_i => clk_dmtd,
clk_sys_o => clk_sys,
clk_aux_i => clk_aux,
clk_ext_i => clk_10mhz,
clk_ext_mul_i => clk_ext_mul_vec,
clk_ext_mul_locked_i=> clk_ext_mul_locked,
clk_aux_p_o => clk_aux_p_o,
......@@ -839,8 +859,10 @@ begin
lj_loopback_o => lj_loopback_o,
lj_clk1_en => lj_clk1_en,
lj_clk2_en => lj_clk2_en,
lj_detected_o => lj_detected,
lj_ext_gm_pll_pres_o => lj_ext_gm_pll_pres,
lj_ext_gm_clk_diff_o => lj_ext_gm_clk_diff,
lj_osc_freq_i => lj_osc_freq_i,
lj_periph_id_i => lj_periph_id_i,
lj_pll_mosi_o => lj_pll_mosi_o,
lj_pll_miso_i => lj_pll_miso_i,
lj_pll_sck_o => lj_pll_sck_o,
......@@ -849,7 +871,6 @@ begin
lj_pll_reset_n_o => lj_pll_reset_n_o,
lj_pll_locked_i => lj_pll_locked_i,
pll_status_i => clk_10mhz,
pll_mosi_o => pll_mosi_o,
pll_miso_i => pll_miso_i,
pll_sck_o => pll_sck_o,
......@@ -861,6 +882,9 @@ begin
clk_en_o => clk_en_o,
clk_sel_o => clk_sel_o,
-- uart_sel_o => uart_sel_o,
wd_int_i => wd_int_i,
wd_scl_i => wd_scl_i,
wd_sda_b => wd_sda_b,
clk_dmtd_divsel_o => clk_dmtd_divsel_o,
gpio_i => x"00000000",
phys_o => to_phys(c_NUM_PORTS-1 downto 0),
......
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