wr_gtx_phy_kintex7_lp: fixed DMTD configuration to match new clock frequencies, more control over resets

The UG382 of Spartan-6 says that the PLLIN of BUFPLL should come from PLL
(CLKOUT0/1) or BUFG. "Banks 1, 3, 4, and 5 can optionally be driven by a
BUFG (O) when using ENABLE_SYNC (FALSE)."

I've tried to modify the setting of ENABLE_SYNC for oserdes_4_to_1/bufpll, but
the 10MHz output is still missing. So I have to change the setting of
"cmp_sys_clk_pll" to make the 500MHz come from CLKOUT1 and clk_ref come from
CLKOUT2.

    change the function of LEDs:
      the front end LEDs display the status of link and sync.
      the on-board LEDS display the act of link and PPS.

    Solve compile bug in ucf file.