- 01 Sep, 2015 9 commits
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Peter Jansweijer authored
added delta delays in phy output signals to line up with the ch#_rx_rbclk_o assignment (purely necessary for proper simulation only)
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Peter Jansweijer authored
when oob.valid, ep_tx_pcs_16bit should (just as ep_tx_psc_8bit) wait for the U_TX_FIFO to empty in order to catch the proper timestamp for the oob signalled packet.
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Peter Jansweijer authored
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Peter Jansweijer authored
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Peter Jansweijer authored
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Peter Jansweijer authored
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Peter Jansweijer authored
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Peter Jansweijer authored
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Grzegorz Daniluk authored
Sometimes *.wb file had to be updated to produce the same result as used till now. Earlier wbgen2 had a problem accepting _align_ for the first field in a register. The bug was fixed, but we want to keep the alignment the old way (already used in the software). Hence I had to delete some of the _align_ directives.
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- 04 Aug, 2015 3 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 03 Aug, 2015 2 commits
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Peter Jansweijer authored
added tx_prbs_sel, sfp_tx_disable, sfp_loss, sfp_tx_fault and full width loopback to MDIO Control register. Be careful: Single bit loopback was relocated to accomodate loopback(2:0)!
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Peter Jansweijer authored
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- 14 Jul, 2015 1 commit
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Grzegorz Daniluk authored
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- 03 Jul, 2015 9 commits
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Grzegorz Daniluk authored
Otherwise, hdlmake complains.
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Grzegorz Daniluk authored
modules/endpoint: count rx frames at the end of rx_path chain and let wr_endpoint decide which one to export It was usefull when debugging the SWcore on high traffic load.
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
When rx buffer is full when new SOF arrives, the whole frame is dropped and not stored in the buffer. However, RTU request was still generated by the ep_rtu_header_extract. This patch prevents ep_rtu_header_extract from generating rtu request, when rxbuf is full on SOF.
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Grzegorz Daniluk authored
phy_rdy_i was needed to fix the Virtex-6 FIFO reseting issue on the WRS. However, WRPC uses inferred fifo which has fully asynchronous reset and does not suffer from this bug. Therefore in case of the WRPC this signal can be tied to '1' or drived from the GTP serdes.
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Grzegorz Daniluk authored
Earlier we were resetting clock alignment fifo (ep_rx_path) when GTX was still not locked and was not producing rx clock. Xilinx document ug363 (Virtex-6 FPGA Memory Resources) says that dual-clock fifo should have reset signal asserted for at least three clock cycles. Chipscope says our fifo was reset while rx clock was not yet there. This apparently was causing Xilinx fifo block going crazy once every few boots. As a result FIFO was asserting _empty_ and _almost_full_ outputs at the same time causing the rx path to stall forever.
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
platform/xilinx: adding rdy_o to gtx and gtp wrappers to indicate when serdes is ready and produces rx clock
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Grzegorz Daniluk authored
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- 12 Feb, 2015 1 commit
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Grzegorz Daniluk authored
If one of them is full, the othe one has to drop a frame as well. Otherwise they are not in sync any more and we have more pfilter decisions than frames or the other way round.
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- 11 Feb, 2015 3 commits
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Grzegorz Daniluk authored
endpoint/rx_vlan_unit: trivial clean-up, removing _old-stuff_ comments, we use git, no need to keep them
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Grzegorz Daniluk authored
endpoint/rx_vlan_unit: when we're storing first fab word in the INSERT_TAG state, it's not necessarily always valid
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Grzegorz Daniluk authored
Previous implementation caused dvalid=1 in Idle state too early in some cases (large traffic) so that the non-valid data word is validated.
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- 10 Feb, 2015 1 commit
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Grzegorz Daniluk authored
If we don't pad 802.1q frames 4-bytes more than regular frames, they become runt frames after untagging (when port is in ACCESS mode).
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- 05 Feb, 2015 1 commit
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Grzegorz Daniluk authored
If there is a storm of frames and rx_buffer gets full it starts to drop frames. However, before this commit even if a frame was dropped that way, U_match_buffer was storing pfilter decision for that frame. As a result decisions coming out from the match_buffer were shifted and applied to wrong frames. With this commit I check if the rx_buffer is full at the beginning of frame and eventually block mbuf_we so that the pfilter decision is not stored.
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- 04 Feb, 2015 1 commit
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Grzegorz Daniluk authored
Otherwise we miss tx timestamp if there is a lot of other traffic.
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- 26 Jan, 2015 1 commit
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Cesar Prados authored
If an external module sends packets from the WR fabric and requests a Tx Ts, the TS were not going to the external IF but to the minic as this packets were sent from the LM32, as a result, the wrpc-sw/ppsi was getting confuse with the PTP TS and ext TS and losing the node synchronization. That was because the TS strobe line was only connected to the minic for every source of TS. This commit mux the stb line depending on the frame_id. For packets sent from LM32 (wrpc-sw) the id is 0x0, packets sent from an external module should use whatever id, but never 0x0.
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- 14 Jan, 2015 4 commits
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Grzegorz Daniluk authored
testbench/wrc_core: improved testbench to send/receive/verify reception frames of every possible size (incl. padded runt frames)
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Grzegorz Daniluk authored
Otherwise, when only part of a frame is received (due to error), decoding oob fails anyway.
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 13 Jan, 2015 4 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Peter Jansweijer authored
If, for some reason, a proper alignment is missed then the cur_slide counter might increment outside its window (0..9 for an 8 bit Phy and 0..19 for a 16 bit Phy). Apparently nobody ever missed an alignment, but it might fail someday, somehow, sometime... Therefore it is wise to put the module function in place. The module function was implemented using an if statement because synthesis tools complained about the VHDL "mod" function.
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Grzegorz Daniluk authored
Conflicts: modules/wrc_core/wr_core.vhd top/spec_1_1/wr_core_demo/spec_top.vhd
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