Commits · bb09df8aa256e01a58d757b08a9cc5ed1fff61e8 · Projects / TimEX3

02 Dec, 2014 1 commit

VHDL : added test bench for the synchronized inhibition of LINAC synchro · bb09df8a

Jean-Paul Ricaud authored Dec 02, 2014

signals ; corrected some bugs

 On branch development

	modified:   fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_synchroInterlock.vhdl
	modified:   fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_top.vhdl
	new file:   fpga/sources/testbench/linacSYNCLOCK_tb.vhdl

bb09df8a

01 Dec, 2014 1 commit

VHDL : the synchronized inhibition of the LINAC SPM / LPM triggers on an · 94502c11

Jean-Paul Ricaud authored Dec 01, 2014

external interlock signal was added to the top level of the TimEX3 FPGA
code

 On branch development

	modified:   fpga/sources/outputmux.vhdl
	modified:   fpga/sources/src_cPCI/cPCI_statusManager.vhdl
	modified:   fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_synchroInterlock.vhdl
	modified:   fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_top.vhdl
	modified:   fpga/sources/top.vhdl

94502c11

28 Nov, 2014 1 commit

VHDL : started the code for a synchronized inhibition of the LINAC SPM · 07682db0

Jean-Paul Ricaud authored Nov 28, 2014

and LPM signals on an external intelock trigger

 On branch development

	modified:   fpga/sources/registers_init.vhdl
	modified:   fpga/sources/src_clkpadding/clkpadding_config.txt
	modified:   fpga/sources/src_duplication/dup_config.txt
	modified:   fpga/sources/src_linacMON/linacMON_top.vhdl
	new file:   fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_config.txt
	new file:   fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_synchroInterlock.vhdl
	new file:   fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_top.vhdl
	modified:   fpga/sources/top.vhdl

07682db0

21 Nov, 2014 1 commit

VHDL : added the option to inhibit the outputs on an external signal for · dc0f3105

Jean-Paul Ricaud authored Nov 21, 2014

the LINAC monotoring function

 On branch development

	modified:   fpga/sources/registers_init.vhdl
	modified:   fpga/sources/src_linacMON/linacMON_config.txt
	new file:   fpga/sources/src_linacMON/linacMON_inhibition.vhdl
	modified:   fpga/sources/src_linacMON/linacMON_top.vhdl
	modified:   fpga/sources/top.vhdl

dc0f3105

08 Oct, 2014 1 commit

DWG : added front panel for clock padding function · b09c456a

Jean-Paul Ricaud authored Oct 08, 2014

 On branch development

	new file:   CAD/TimEX3_clkpadding-FP.dwg
	modified:   fpga/sources/src_clkpadding/clkpadding_config.txt
	modified:   fpga/sources/src_clkpadding/clkpadding_top.vhdl

b09c456a

06 Oct, 2014 1 commit

VHDL : corrected padding function · 4810e869

Jean-Paul Ricaud authored Oct 06, 2014

 On branch development

	modified:   fpga/sources/src_clkpadding/clkpadding_top.vhdl
	new file:   fpga/sources/testbench/clkpadding_tb.vhdl
	modified:   fpga/sources/top.vhdl

4810e869

22 Sep, 2014 1 commit

VHDL : added clock padding for CRISTAL beamline laser · 2d45d219

Jean-Paul Ricaud authored Sep 22, 2014

 On branch development

	modified:   fpga/sources/outputmux.vhdl
	modified:   fpga/sources/registers_init.vhdl
	new file:   fpga/sources/src_clkpadding/clkpadding_config.txt
	new file:   fpga/sources/src_clkpadding/clkpadding_top.vhdl
	modified:   fpga/sources/src_topup/topup_top.vhdl
	modified:   fpga/sources/top.vhdl

2d45d219

07 Mar, 2014 1 commit

Added CAD drawing for frequency divider option and binaries files. · 618e1548

Jean-Paul Ricaud authored Mar 07, 2014

 On branch master

	new file:   CAD/TimEX3_freqDiv-FP.dwg
	modified:   fpga/TimEX3/TimEX3_eeprom.mcs
	modified:   fpga/sources/src_freqDIV/freqDIV_config.txt

618e1548

07 Feb, 2014 1 commit

VHDL : added frequency divider block for slicing synchro DG · 4563b9be

Jean-Paul Ricaud authored Feb 07, 2014

 On branch development

	modified:   fpga/sources/outputmux.vhdl
	modified:   fpga/sources/registers_init.vhdl
	modified:   fpga/sources/src_cPCI/cPCI_registerMux.vhdl
	modified:   fpga/sources/src_cPCI/cPCI_statusManager.vhdl
	modified:   fpga/sources/src_duplication/dup_leds.vhdl
	new file:   fpga/sources/src_freqDIV/freqDIV_clkdiv.vhdl
	new file:   fpga/sources/src_freqDIV/freqDIV_config.txt
	new file:   fpga/sources/src_freqDIV/freqDIV_leds.vhdl
	new file:   fpga/sources/src_freqDIV/freqDIV_monitoring.vhdl
	new file:   fpga/sources/src_freqDIV/freqDIV_top.vhdl
	modified:   fpga/sources/src_linacMON/linacMON_leds.vhdl
	modified:   fpga/sources/src_linacMP/linacMP_leds.vhdl
	modified:   fpga/sources/src_topup/topup_beamlost.vhdl
	modified:   fpga/sources/src_topup/topup_gating.vhdl
	modified:   fpga/sources/top.vhdl
	modified:   fpga/sources/type_lib.vhdl

4563b9be

09 Jan, 2014 1 commit
- VHDL : corrected an error in the comment of the status register · f505d678
  Jean-Paul Ricaud authored Jan 09, 2014
```
 On branch development

	modified:   fpga/sources/top.vhdl
```
  f505d678
09 Dec, 2013 1 commit

VHDL : code cleanup · 28062311

Jean-Paul Ricaud authored Dec 09, 2013

 On branch development

	modified:   fpga/TimEX3/TimEX3_eeprom.mcs
	modified:   fpga/sources/registers_init.vhdl
	modified:   fpga/sources/src_cPCI/cPCI_hermes.vhdl
	modified:   fpga/sources/src_cPCI/cPCI_hermes_registers.vhdl
	modified:   fpga/sources/src_cPCI/cPCI_registerMux.vhdl
	modified:   fpga/sources/top.vhdl
	new file:   fpga/sources/type_lib.vhdl

28062311

29 Nov, 2013 1 commit

VHDL : Monitoring now reacts on rising edge of the signal instead of high level · 686fe9ce

Jean-Paul Ricaud authored Nov 29, 2013

 On branch development

	modified:   fpga/TimEX3/TimEX3_eeprom.mcs
	modified:   fpga/sources/src_duplication/dup_leds.vhdl
	modified:   fpga/sources/src_duplication/dup_monitoring.vhdl
	modified:   fpga/sources/src_linacMON/linacMON_leds.vhdl
	modified:   fpga/sources/src_linacMON/linacMON_monitoring.vhdl
	modified:   fpga/sources/src_linacMP/linacMP_leds.vhdl
	modified:   fpga/sources/src_linacMP/linacMP_monitoring.vhdl
	modified:   fpga/sources/top.vhdl

686fe9ce

28 Nov, 2013 1 commit

VHDL : corrected a bug in status manager · 8ee6950d

Jean-Paul Ricaud authored Nov 28, 2013

 On branch development

	modified:   fpga/TimEX3/TimEX3_eeprom.mcs
	modified:   fpga/sources/src_cPCI/cPCI_statusManager.vhdl

8ee6950d

27 Nov, 2013 1 commit

VHDL : multiplexed cPCI registers to overlap data depending on the configuration… · 1e2013e4

Jean-Paul Ricaud authored Nov 27, 2013

VHDL : multiplexed cPCI registers to overlap data depending on the configuration (duplication, top-up, etc.)

 On branch development

	modified:   fpga/TimEX3/TimEX3_eeprom.mcs
	modified:   fpga/sources/registers_init.vhdl
	modified:   fpga/sources/src_cPCI/cPCI_hermes.vhdl
	modified:   fpga/sources/src_cPCI/cPCI_registerMux.vhdl
	modified:   fpga/sources/src_cPCI/cPCI_statusManager.vhdl
	modified:   fpga/sources/top.vhdl

1e2013e4

19 Nov, 2013 1 commit

VHDL : Multiplexed cPCI registers to overlap them depending on the configuration… · ffdb6900

Jean-Paul Ricaud authored Nov 19, 2013

VHDL : Multiplexed cPCI registers to overlap them depending on the configuration (duplication, top-up, etc.)

 On branch development

	modified:   fpga/sources/registers_init.vhdl
	new file:   fpga/sources/src_cPCI/cPCI_registerMux.vhdl
	modified:   fpga/sources/src_cPCI/cPCI_statusManager.vhdl
	modified:   fpga/sources/top.vhdl

ffdb6900

13 Nov, 2013 1 commit

Updated EEPROM with version v1.4.1 · 0a760e9a

Jean-Paul Ricaud authored Nov 13, 2013

 On branch development

	modified:   fpga/TimEX3/TimEX3_eeprom.mcs
	modified:   fpga/sources/top.vhdl

0a760e9a

12 Nov, 2013 1 commit

VHDL : Added a register to read the configuration of the board · 440e4087

Jean-Paul Ricaud authored Nov 12, 2013

(duplication, top-up, etc.).

 On branch development

	modified:   fpga/sources/src_cPCI/cPCI_hermes.vhdl
	modified:   fpga/sources/src_cPCI/cPCI_hermes_registers.vhdl
	modified:   fpga/sources/top.vhdl

440e4087

06 Nov, 2013 1 commit

VHDL : Set a bit during 2s after a top-up injection window or a beam lost… · 679ffb3d

Jean-Paul Ricaud authored Nov 06, 2013

VHDL : Set a bit during 2s after a top-up injection window or a beam lost window. The bit will be set for window width duration + 2s, those it can be read by polling through the software

On branch development

new file: fpga/sources/src_topup/topup_stateBit.vhdl
modified: fpga/sources/src_topup/topup_top.vhdl
modified: fpga/sources/top.vhdl

679ffb3d

29 Oct, 2013 1 commit

VHDL : added the state of the gating windows in the status register · 1c10ca7a

Jean-Paul Ricaud authored Oct 29, 2013

 On branch development

	modified:   fpga/TimEX3/top.ucf
	modified:   fpga/sources/registers_init.vhdl
	modified:   fpga/sources/src_topup/topup_beamlost.vhdl
	modified:   fpga/sources/src_topup/topup_gating.vhdl
	modified:   fpga/sources/src_topup/topup_top.vhdl
	modified:   fpga/sources/top.vhdl

1c10ca7a

09 Aug, 2013 1 commit
- FPGA : updated the EEPROM binairies with LINAC functions · 8e21f2e8
  Jean-Paul Ricaud authored Aug 09, 2013
```
 On branch development

	modified:   fpga/TimEX3/TimEX3_eeprom.mcs
```
  8e21f2e8
31 Jul, 2013 1 commit

VHDL : modification of the LINAC SPM monitoring to take into account 10 · 8fce8630

Jean-Paul Ricaud authored Jul 31, 2013

ns pulses

 On branch development

	modified:   fpga/sources/src_linacMON/linacMON_monitoring.vhdl
	modified:   fpga/sources/src_linacMON/linacMON_simTrigg.vhdl

8fce8630

10 Jul, 2013 1 commit

VHDL : added LINAC monitoring function · f9cb50e1

Jean-Paul Ricaud authored Jul 10, 2013

 On branch development

	new file:   CAD/TimEX3_linacDT-FP.dwg
	new file:   CAD/TimEX3_linacMP-FP.dwg
	modified:   fpga/sources/outputmux.vhdl
	modified:   fpga/sources/registers_init.vhdl
	new file:   fpga/sources/src_linacMON/linacMON_config.txt
	new file:   fpga/sources/src_linacMON/linacMON_leds.vhdl
	new file:   fpga/sources/src_linacMON/linacMON_monitoring.vhdl
	new file:   fpga/sources/src_linacMON/linacMON_simTrigg.vhdl
	new file:   fpga/sources/src_linacMON/linacMON_top.vhdl
	modified:   fpga/sources/src_linacMP/linacMP_config.txt
	renamed:    fpga/sources/src_linacMP/linacMP_andpulses.vhdl -> fpga/sources/src_linacMP/linacMP_orpulses.vhdl
	modified:   fpga/sources/src_linacMP/linacMP_top.vhdl
	modified:   fpga/sources/top.vhdl

f9cb50e1

17 Jun, 2013 1 commit

VHDL : Compensated output offsets in duplication mode · 5182c64f

Jean-Paul Ricaud authored Jun 17, 2013

 On branch development

	modified:   fpga/TimEX3/TimEX3_eeprom.mcs
	new file:   fpga/TimEX3/keep.ncd
	modified:   fpga/sources/registers_init.vhdl
	modified:   fpga/sources/src_duplication/dup_top.vhdl
	modified:   fpga/sources/src_topup/topup_beamlost.vhdl

5182c64f

12 Jun, 2013 1 commit

VHDL : added a reset impulse on rising edge of pre top-up signal to · b523d04e

Jean-Paul Ricaud authored Jun 12, 2013

reset the beam lost cycle ; cleaned comments and signal names

 On branch development

	modified:   fpga/sources/registers_init.vhdl
	modified:   fpga/sources/src_topup/topup_beamlost.vhdl
	modified:   fpga/sources/src_topup/topup_top.vhdl
	modified:   fpga/sources/top.vhdl

b523d04e

30 Apr, 2013 1 commit

VHDL : corrected comments of the top-up gating · b5fc43b9

Jean-Paul Ricaud authored Apr 30, 2013

 On branch development

	modified:   fpga/sources/src_topup/topup_gating.vhdl
	modified:   fpga/sources/top.vhdl

b5fc43b9

26 Apr, 2013 2 commits

VHDL : updated the topup_config.txt file to reflect the new outputs · 00d1ee91
Jean-Paul Ricaud authored Apr 26, 2013
```
configuration

 On branch development

	modified:   fpga/sources/src_topup/topup_config.txt
```
00d1ee91

VHDL : added beam lost monitoring. In top-up gating mode, the outputs of · 3cf46b9a

Jean-Paul Ricaud authored Apr 26, 2013

the board are now configured as :

output(2) : negative gating window
output(3) : negative beam lost
output(4) : negative (beam lost + gating) window

 On branch development

	modified:   fpga/TimEX3/TimEX3_eeprom.mcs
	modified:   fpga/TimEX3/top.ucf
	modified:   fpga/sources/src_topup/topup_beamlost.vhdl
	modified:   fpga/sources/src_topup/topup_leds.vhdl
	modified:   fpga/sources/src_topup/topup_top.vhdl

3cf46b9a

12 Apr, 2013 1 commit

VHDL : corrected a error in top-up gating module ; changed the · bfae43b6

Jean-Paul Ricaud authored Apr 12, 2013

monitoring to monitor and gate a beam lost

 On branch development

	modified:   fpga/sources/registers_init.vhdl
	new file:   fpga/sources/src_topup/topup_beamlost.vhdl
	modified:   fpga/sources/src_topup/topup_gating.vhdl
	new file:   fpga/sources/src_topup/topup_injError.vhdl
	modified:   fpga/sources/src_topup/topup_leds.vhdl
	deleted:    fpga/sources/src_topup/topup_monitor.vhdl
	modified:   fpga/sources/src_topup/topup_top.vhdl
	modified:   fpga/sources/top.vhdl

bfae43b6

09 Apr, 2013 1 commit

typo correction · c012f785

Jean-Paul Ricaud authored Apr 09, 2013

 On branch development

	modified:   fpga/sources/src_topup/topup_config.txt

c012f785

19 Mar, 2013 1 commit
- VHDL : adjusted the top-up holdoff value · a2e3bca4
  Jean-Paul Ricaud authored Mar 19, 2013
```
 On branch development

	modified:   fpga/sources/registers_init.vhdl
```
  a2e3bca4
18 Mar, 2013 1 commit

VHDL : added LINAC multi-pulse function · 69f29835

Jean-Paul Ricaud authored Mar 18, 2013

SCH : corrected typo error

 On branch development

	modified:   fpga/sources/outputmux.vhdl
	modified:   fpga/sources/registers_init.vhdl
	modified:   fpga/sources/src_duplication/dup_config.txt
	modified:   fpga/sources/src_duplication/dup_leds.vhdl
	modified:   fpga/sources/src_duplication/dup_monitoring.vhdl
	modified:   fpga/sources/src_duplication/dup_top.vhdl
	new file:   fpga/sources/src_linacMP/linacMP_andpulses.vhdl
	new file:   fpga/sources/src_linacMP/linacMP_config.txt
	new file:   fpga/sources/src_linacMP/linacMP_leds.vhdl
	new file:   fpga/sources/src_linacMP/linacMP_monitoring.vhdl
	new file:   fpga/sources/src_linacMP/linacMP_top.vhdl
	modified:   fpga/sources/src_test/test_config.txt
	modified:   fpga/sources/src_topup/topup_config.txt
	modified:   fpga/sources/top.vhdl
	modified:   sch/Expansion_connectors.sch
	modified:   sch/FPGA.sch
	modified:   sch/FPGA_config.sch
	modified:   sch/Osc.sch
	modified:   sch/PCI9030.sch
	modified:   sch/cPCI_connector.sch
	modified:   sch/input.sch
	modified:   sch/outputs.sch
	modified:   sch/psu.sch
	modified:   sch/reset.sch
	modified:   sch/timex3_sch-cache.lib
	modified:   sch/timex3_sch.pro
	modified:   sch/timex3_sch.sch
	modified:   sch/top.sch

69f29835

14 Mar, 2013 1 commit

SCH : replaced C2 ; C 11 ; C12 C13 & C14 by 0R (better ligne adaptation) · 5fc0ff0a

Jean-Paul Ricaud authored Mar 14, 2013

 On branch development

	modified:   sch/Expansion_connectors.sch
	modified:   sch/FPGA.sch
	modified:   sch/FPGA_config.sch
	modified:   sch/Osc.sch
	modified:   sch/PCI9030.sch
	modified:   sch/bom_TTL.xlsx
	modified:   sch/cPCI_connector.sch
	modified:   sch/input.sch
	modified:   sch/outputs.sch
	modified:   sch/psu.sch
	modified:   sch/reset.sch
	modified:   sch/timex3_sch-cache.lib
	modified:   sch/timex3_sch.sch
	modified:   sch/top.sch

5fc0ff0a

13 Mar, 2013 1 commit

VHDL : changed the time base of duplication monitor to 1 ms ; added some · 0c5e42bb

Jean-Paul Ricaud authored Mar 13, 2013

signal to improve the skew
CAD : changed the names OUT1 -> OUT0 ; OUT2 -> OUT1 ; OUT3 -> OUT2 ;
OUT4 -> OUT3

 On branch development

	renamed:    cao/TimEX3_TTL-FP.dwg -> CAD/TimEX3_TTL-FP.dwg
	renamed:    cao/TimEX3_gating-FP.dwg -> CAD/TimEX3_gating-FP.dwg
	modified:   fpga/TimEX3/TimEX3_eeprom.mcs
	modified:   fpga/TimEX3/top.ucf
	modified:   fpga/sources/src_duplication/dup_duplication.vhdl
	modified:   fpga/sources/src_duplication/dup_leds.vhdl
	modified:   fpga/sources/src_duplication/dup_top.vhdl

0c5e42bb

11 Mar, 2013 1 commit

VHDL : changed the time base to 1 kHz ; corrected an unconnected port ; · 96438d55

Jean-Paul Ricaud authored Mar 11, 2013

corrected an unreliable equality

 On branch development

	modified:   fpga/sources/clk_sources.vhdl
	modified:   fpga/sources/registers_init.vhdl
	modified:   fpga/sources/src_duplication/dup_monitoring.vhdl
	modified:   fpga/sources/src_duplication/dup_top.vhdl
	modified:   fpga/sources/src_topup/topup_gating.vhdl
	modified:   fpga/sources/src_topup/topup_leds.vhdl
	modified:   fpga/sources/src_topup/topup_monitor.vhdl
	modified:   fpga/sources/src_topup/topup_top.vhdl
	modified:   fpga/sources/testbench/clk_sources_tb.vhdl
	modified:   fpga/sources/testbench/dup_top_tb.vhdl
	modified:   fpga/sources/testbench/topup_gating_tb.vhdl
	modified:   fpga/sources/testbench/topup_monitor_tb.vhdl
	modified:   fpga/sources/top.vhdl

96438d55

07 Mar, 2013 1 commit

VHDL : corrected an error in addresses of the cPCI registers ; Added a · 1f60834a

Jean-Paul Ricaud authored Mar 07, 2013

file with initial value of registers

 On branch development

	modified:   fpga/TimEX3/TimEX3_eeprom.mcs
	new file:   fpga/sources/registers_init.vhdl
	modified:   fpga/sources/src_cPCI/cPCI_hermes.vhdl
	modified:   fpga/sources/src_cPCI/cPCI_hermes_registers.vhdl
	modified:   fpga/sources/src_cPCI/cPCI_statusManager.vhdl
	modified:   fpga/sources/src_duplication/dup_leds.vhdl
	modified:   fpga/sources/src_topup/topup_gating.vhdl
	modified:   fpga/sources/src_topup/topup_monitor.vhdl
	modified:   fpga/sources/top.vhdl

1f60834a

06 Mar, 2013 1 commit
- VHDL : corrected a error in top module ; added more comment on registers · 6f6643a7
  Jean-Paul Ricaud authored Mar 06, 2013
```
 On branch development

	modified:   fpga/TimEX3/TimEX3_eeprom.mcs
	modified:   fpga/sources/top.vhdl
```
  6f6643a7
05 Mar, 2013 1 commit
- Added PLX9030 EEPROM binaries · 0722e3ec
  Jean-Paul Ricaud authored Mar 05, 2013
```
 On branch development

	new file:   cPCI/TIMEX3_PLX_EEPROM.eep
```
  0722e3ec
01 Mar, 2013 2 commits
- VHDL : added reset in sensibility list in clk_sources.vhdl ; switched to · 798f3542
  Jean-Paul Ricaud authored Mar 01, 2013
```
PlanAhead as it's what we should do

 On branch development

	modified:   fpga/TimEX3/top.ucf
	modified:   fpga/sources/clk_sources.vhdl
```
  798f3542
- VHDL : coorected typo error in topup_top.vhdl · 60adf687
  Jean-Paul Ricaud authored Mar 01, 2013
```
 On branch development

	modified:   fpga/sources/src_topup/topup_top.vhdl
```
  60adf687
28 Feb, 2013 1 commit

VHDL : modified repertories names ; corrected clk source ; corrected · 01dec940

Jean-Paul Ricaud authored Feb 28, 2013

top-up monitoring

On branch development

modified: fpga/sources/clk_sources.vhdl
renamed: fpga/sources/cPCI/cPCI_hermes.vhdl -> fpga/sources/src_cPCI/cPCI_hermes.vhdl
renamed: fpga/sources/cPCI/cPCI_hermes_registers.vhdl -> fpga/sources/src_cPCI/cPCI_hermes_registers.vhdl
renamed: fpga/sources/cPCI/cPCI_statusManager.vhdl -> fpga/sources/src_cPCI/cPCI_statusManager.vhdl
renamed: fpga/sources/source_duplication/dup_config.txt -> fpga/sources/src_duplication/dup_config.txt
renamed: fpga/sources/source_duplication/dup_duplication.vhdl -> fpga/sources/src_duplication/dup_duplication.vhdl
renamed: fpga/sources/source_duplication/dup_leds.vhdl -> fpga/sources/src_duplication/dup_leds.vhdl
renamed: fpga/sources/source_duplication/dup_monitoring.vhdl -> fpga/sources/src_duplication/dup_monitoring.vhdl
renamed: fpga/sources/source_duplication/dup_top.vhdl -> fpga/sources/src_duplication/dup_top.vhdl
renamed: fpga/sources/test/test_config.txt -> fpga/sources/src_test/test_config.txt
renamed: fpga/sources/test/test_top.vhdl -> fpga/sources/src_test/test_top.vhdl
renamed: fpga/sources/source_topup/topup_config.txt -> fpga/sources/src_topup/topup_config.txt
renamed: fpga/sources/source_topup/topup_gating.vhdl -> fpga/sources/src_topup/topup_gating.vhdl
renamed: fpga/sources/source_topup/topup_leds.vhdl -> fpga/sources/src_topup/topup_leds.vhdl
renamed: fpga/sources/source_topup/topup_monitor.vhdl -> fpga/sources/src_topup/topup_monitor.vhdl
renamed: fpga/sources/source_topup/topup_top.vhdl -> fpga/sources/src_topup/topup_top.vhdl
modified: fpga/sources/top.vhdl

01dec940