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TimEX3
Commit 94502c11 authored by Jean-Paul Ricaud's avatar Jean-Paul Ricaud
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VHDL : the synchronized inhibition of the LINAC SPM / LPM triggers on an 

external interlock signal was added to the top level of the TimEX3 FPGA
code

 On branch development

	modified:   fpga/sources/outputmux.vhdl
	modified:   fpga/sources/src_cPCI/cPCI_statusManager.vhdl
	modified:   fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_synchroInterlock.vhdl
	modified:   fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_top.vhdl
	modified:   fpga/sources/top.vhdl
parent 07682db0
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Showing with 118 additions and 86 deletions
fpga/sources/outputmux.vhdl
View file @ 94502c11
......@@ -6,7 +6,7 @@
-- SW 5-4-3-2-1-0
-- 1-1-1-1-1-1 : board test
-- 0-0-0-1-1-0 : clock padding
-- 0-0-0-1-0-1 : LINAC inhibition
-- 0-0-0-1-0-1 : LINAC synchonized interlock
-- 0-0-0-1-0-0 : frequency divider
-- 0-0-0-0-1-1 : LINAC monitoring
-- 0-0-0-0-1-0 : LINAC multipulse
......@@ -16,7 +16,7 @@
-- File : outputmux.vhdl
-- Revision : x.x.x
-- Created : October 26, 2012
-- Updated : November 28, 2014
-- Updated : December 01, 2014
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -50,7 +50,7 @@
-- Version 1.9.0 ; November 28 2014 ; Jean-Paul Ricaud
-- * Changed the configuration switch of the clock padding from
-- 0-0-0-1-0-1 to 0-0-0-1-1-0
-- * Added inhibition of the LINAC synchronization signals
-- * Added synchronized interlock of the LINAC's synchronization signals
--
--------------------------------------------------------------------------------
......@@ -83,6 +83,10 @@ entity outputMux is
p_freqDIV_outTTL : in std_logic_vector (4 downto 0);
p_freqDIV_outPECL : in std_logic_vector (4 downto 0);
p_freqDIV_LED : in std_logic_vector (1 downto 0);
-- LINAC synchronized interlock block
p_linacSYNCLOCK_outTTL : in std_logic_vector (4 downto 0);
p_linacSYNCLOCK_outPECL : in std_logic_vector (4 downto 0);
p_linacSYNCLOCK_LED : in std_logic_vector (1 downto 0);
-- clock padding block
p_clkPADDING_outTTL : in std_logic_vector (4 downto 0);
p_clkPADDING_outPECL : in std_logic_vector (4 downto 0);
......@@ -123,35 +127,38 @@ architecture rtl_outputMux of outputMux is
-- TTL ouuputs selection
with p_mux_SWsel select
p_mux_outTTL <=
p_dup_outTTL when "000000",
p_topUp_outTTL when "000001",
p_linacMP_outTTL when "000010",
p_linacMON_outTTL when "000011",
p_freqDIV_outTTL when "000100",
p_clkPADDING_outTTL when "000110",
p_test_outTTL when OTHERS;
p_dup_outTTL when "000000",
p_topUp_outTTL when "000001",
p_linacMP_outTTL when "000010",
p_linacMON_outTTL when "000011",
p_freqDIV_outTTL when "000100",
p_linacSYNCLOCK_outTTL when "000101",
p_clkPADDING_outTTL when "000110",
p_test_outTTL when OTHERS;
-- LVPECL ouuputs selection
with p_mux_SWsel select
p_mux_outPECL <=
p_dup_outPECL when "000000",
p_topUp_outPECL when "000001",
p_linacMP_outPECL when "000010",
p_linacMON_outPECL when "000011",
p_freqDIV_outPECL when "000100",
p_clkPADDING_outPECL when "000110",
p_test_outPECL when OTHERS;
p_dup_outPECL when "000000",
p_topUp_outPECL when "000001",
p_linacMP_outPECL when "000010",
p_linacMON_outPECL when "000011",
p_freqDIV_outPECL when "000100",
p_linacSYNCLOCK_outPECL when "000101",
p_clkPADDING_outPECL when "000110",
p_test_outPECL when OTHERS;
-- LEDs outputs selection
with p_mux_SWsel select
p_mux_outLED <=
p_dup_LED when "000000",
p_topUp_LED when "000001",
p_linacMP_LED when "000010",
p_linacMON_LED when "000011",
p_freqDIV_LED when "000100",
p_clkPADDING_LED when "000110",
p_test_LED when OTHERS;
p_dup_LED when "000000",
p_topUp_LED when "000001",
p_linacMP_LED when "000010",
p_linacMON_LED when "000011",
p_freqDIV_LED when "000100",
p_linacSYNCLOCK_LED when "000101",
p_clkPADDING_LED when "000110",
p_test_LED when OTHERS;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
......
fpga/sources/src_cPCI/cPCI_statusManager.vhdl
View file @ 94502c11
......@@ -9,7 +9,7 @@
-- File : cPCI_statusManager.vhdl
-- Revision : x.x.x
-- Created : December 05, 2012
-- Updated : February 03, 2014
-- Updated : December 01, 2014
-------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -49,7 +49,7 @@ use work.registers_init.all;
-------------------------------------------------------------------------------
entity cPCI_statusManager is
port (
p_inStates : in std_logic_vector (9 downto 0);
p_inStates : in std_logic_vector (10 downto 0);
p_status : out std_logic_vector (29 downto 0);
p_cfgSW : in std_logic_vector (5 downto 0);
p_clk60MHz : in std_logic;
......@@ -90,6 +90,7 @@ architecture rtl_cPCI_statusManager of cPCI_statusManager is
when "000010" => s_status <= "000000000" & p_inStates(5);
when "000011" => s_status <= "0000000" & p_inStates(8 downto 6);
when "000100" => s_status <= "000000000" & p_inStates(9);
when "000101" => s_status <= "000000000" & p_inStates(10);
when others => s_status <= "0000000000";
end case;
end if;
......
fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_synchroInterlock.vhdl
View file @ 94502c11
......@@ -10,7 +10,7 @@
-- File : linacSYNCLOCK_synchroInterlock.vhdl
-- Revision : x.x.x
-- Created : November 28, 2014
-- Updated : November 28, 2014
-- Updated : December 01, 2014
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -54,7 +54,7 @@ entity linacSYNCLOCK_synchroInterlock is
p_clk60MHz : in std_logic;
p_precharge : in std_logic;
p_interlock : in std_logic;
p_synchroInterlock : out std_logic
p_synchroInterlock : out std_logic -- O = inhibit outputs
);
end entity linacSYNCLOCK_synchroInterlock;
......@@ -66,14 +66,14 @@ architecture rtl_linacSYNCLOCK_synchroInterlock of linacSYNCLOCK_synchroInterloc
------------------------------------------------------------------------------
-- constant
------------------------------------------------------------------------------
constant s_cntmax_precharge : unsigned (20 downto 0) := X"12380F";
constant s_cntmax_freeze : unsigned (12 downto 0) := X"176E";
constant c_cntmax_precharge : unsigned (23 downto 0) := X"12380F";
constant c_cntmax_freeze : unsigned (15 downto 0) := X"176E";
------------------------------------------------------------------------------
-- signal
------------------------------------------------------------------------------
signal s_cnt_precharge : unsigned (31 downto 0); -- countdown from precharge
signal s_cnt_freez : unsigned (12 downto 0); -- freez interlock counter
signal s_cnt_precharge : unsigned (23 downto 0); -- countdown from precharge
signal s_cnt_freez : unsigned (15 downto 0); -- freez interlock counter
signal s_start_contdown : std_logic;
signal s_start_freez : std_logic;
signal s_end_freez : std_logic;
......@@ -107,14 +107,14 @@ architecture rtl_linacSYNCLOCK_synchroInterlock of linacSYNCLOCK_synchroInterloc
elsif (rising_edge(p_clk60MHz)) then
if (s_start_contdown = '1') then
s_cnt_precharge <= s_cnt_precharge + 1;
if (s_cnt_precharge > s_cntmax_precharge) then
if (s_cnt_precharge > c_cntmax_precharge) then
s_start_freez <= '1';
end if;
end if;
end if;
end process;
-- Stop the freez after the freez timeout
-- Stop freezing after the freez timeout
process (s_reset, p_clk60MHz)
begin
if (s_reset = '1') then
......@@ -123,7 +123,7 @@ architecture rtl_linacSYNCLOCK_synchroInterlock of linacSYNCLOCK_synchroInterloc
elsif (rising_edge(p_clk60MHz)) then
if (s_start_freez = '1') then
s_cnt_freez <= s_cnt_freez + 1;
if (s_cnt_freez > s_cntmax_freez) then
if (s_cnt_freez > c_cntmax_freeze) then
s_end_freez <= '1';
end if;
end if;
......@@ -138,7 +138,7 @@ architecture rtl_linacSYNCLOCK_synchroInterlock of linacSYNCLOCK_synchroInterloc
elsif (rising_edge(p_clk60MHz)) then
if (s_end_freez = '1') then
s_reset_stats <= '1';
elsif
else
s_reset_stats <= '0';
end if;
end if;
......@@ -152,7 +152,7 @@ architecture rtl_linacSYNCLOCK_synchroInterlock of linacSYNCLOCK_synchroInterloc
elsif (rising_edge(p_clk60MHz)) then
if (s_start_freez = '1') then
s_inhibition <= s_inhibition; -- freezed
elsif
else
s_inhibition <= p_interlock; -- follows the interlock
end if;
end if;
......
fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_top.vhdl
View file @ 94502c11
......@@ -20,7 +20,7 @@
-- File : linacSYNCLOCK_top.vhdl
-- Revision : x.x.x
-- Created : November 28, 2014
-- Updated : November 28, 2014
-- Updated : December 01, 2014
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -57,15 +57,13 @@ use ieee.numeric_std.all;
--------------------------------------------------------------------------------
entity linacSYNCLOCK_top is
port (
p_linacSYNCLOCK_inTTL : in std_logic_vector (1 downto 0); -- TTL inputs
p_linacSYNCLOCK_outTTL : out std_logic_vector (4 downto 0); -- TTL outputs
p_linacSYNCLOCK_outPECL : out std_logic_vector (4 downto 0); -- LVPECL outputs
p_linacSYNCLOCK_clk1kHz : in std_logic;
p_linacSYNCLOCK_clk500mHz : in std_logic;
p_linacSYNCLOCK_clk60MHz : in std_logic;
p_linacSYNCLOCK_reset : in std_logic;
p_linacSYNCLOCK_state : out std_logic_vector (31 downto 0); -- interlock state
p_linacSYNCLOCK_led : out std_logic_vector (1 downto 0)
p_linacSYNCLOCK_inTTL : in std_logic_vector (1 downto 0); -- TTL inputs
p_linacSYNCLOCK_outTTL : out std_logic_vector (4 downto 0); -- TTL outputs
p_linacSYNCLOCK_outPECL : out std_logic_vector (4 downto 0); -- LVPECL outputs
p_linacSYNCLOCK_clk60MHz : in std_logic;
p_linacSYNCLOCK_reset : in std_logic;
p_linacSYNCLOCK_state : out std_logic; -- interlock state ; 1 = interlock ON
p_linacSYNCLOCK_led : out std_logic_vector (1 downto 0)
);
end entity linacSYNCLOCK_top;
......@@ -101,7 +99,7 @@ architecture rtl_linacSYNCLOCK_top of linacSYNCLOCK_top is
end if;
end process;
-- Synchronize the interlock sygnal to the injection / extraction cycles
-- Synchronize the interlock signal to the injection / extraction cycles
synchroInterlock : entity work.linacSYNCLOCK_synchroInterlock (rtl_linacSYNCLOCK_synchroInterlock)
port map (
p_reset => p_linacSYNCLOCK_reset,
......@@ -109,15 +107,16 @@ architecture rtl_linacSYNCLOCK_top of linacSYNCLOCK_top is
p_precharge => p_linacSYNCLOCK_inTTL(0), -- pre-charge event
p_interlock => s_holdInterlock(2), -- interlock signal
p_synchroInterlock => s_linacSYNCLOCK_synchro_interlock -- synchronized interlock signal
-- 0 = inhibited
);
-- Push the state of the interlock in the register
process (p_linacSYNCLOCK_clk60MHz, p_linacSYNCLOCK_reset)
begin
if (p_linacSYNCLOCK_reset = '1') then
p_linacSYNCLOCK_state <= (OTHERS => '0');
p_linacSYNCLOCK_state <= '0';
elsif (falling_edge(p_linacSYNCLOCK_clk60MHz)) then
p_linacSYNCLOCK_state(0) <= not s_linacSYNCLOCK_synchro_interlock;
p_linacSYNCLOCK_state <= not s_linacSYNCLOCK_synchro_interlock;
end if;
end process;
......
fpga/sources/top.vhdl
View file @ 94502c11
......@@ -7,7 +7,7 @@
-- File : top.vhd
-- Revision : x.x.x
-- Created : October 26, 2012
-- Updated : November 28, 2014
-- Updated : December 01, 2014
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -54,7 +54,7 @@
-- Version 1.9.0 ; November 28 2014 ; Jean-Paul Ricaud
-- * Changed the configuration switch of the clock padding from
-- 0-0-0-1-0-1 to 0-0-0-1-1-0
-- * Added inhibition of the LINAC synchronization signals
-- * Added synchronized interlock of the LINAC's synchronization signals
--
--------------------------------------------------------------------------------
......@@ -186,21 +186,27 @@ architecture rtl_top of top is
signal s_linacMONLED : std_logic_vector (1 downto 0);
signal s_linacMONdelayError : std_logic_vector (1 downto 0);
-- Topup signals
signal s_testOutTTL : std_logic_vector (4 downto 0);
signal s_testOutPECL : std_logic_vector (4 downto 0);
signal s_testLED : std_logic_vector (1 downto 0);
-- Frequency divider signals
signal s_freqDivOutTTL : std_logic_vector (4 downto 0);
signal s_freqDivOutPECL : std_logic_vector (4 downto 0);
signal s_freqDivLED : std_logic_vector (1 downto 0);
-- LINAC synchronized interlock block
signal s_linacSYNCLOCKOutTTL : std_logic_vector (4 downto 0);
signal s_linacSYNCLOCKOutPECL : std_logic_vector (4 downto 0);
signal s_linacSYNCLOCKstate : std_logic;
signal s_linacSYNCLOCKLED : std_logic_vector (1 downto 0);
-- Clock padding signals
signal s_clkPaddingOutTTL : std_logic_vector (4 downto 0);
signal s_clkPaddingOutPECL : std_logic_vector (4 downto 0);
signal s_clkPaddingLED : std_logic_vector (1 downto 0);
-- Test signals
signal s_testOutTTL : std_logic_vector (4 downto 0);
signal s_testOutPECL : std_logic_vector (4 downto 0);
signal s_testLED : std_logic_vector (1 downto 0);
------------------------------------------------------------------------------
-- Attributes
------------------------------------------------------------------------------
......@@ -408,23 +414,26 @@ architecture rtl_top of top is
-- Status(2) set : simultaneous SPM / LPM [LINAC monitoring mode]
-- *** Frequency divider ***
-- Status(0) set : time between 2 CLK_SR pulses exceeded the maximum delay [frequency divider mode]
-- *** LINAC synchronized interlock ***
-- Status(0) set : interlock signal is ON [LINAC synchronized interlock mode]
cPCI_status: entity work.cPCI_statusManager (rtl_cPCI_statusManager)
port map (
p_inStates(0) => s_dupLED(0), -- time between 2 synchro pulses exceeded the maximum delay
p_inStates(1) => s_topUpTopUpGate(0), -- top-up gated (1 : window active)
p_inStates(2) => s_topUpBeamLostGate(0), -- beam lost gated (1 : window active)
p_inStates(3) => s_topUpTopUpGate(1), -- top-up gated (1 : window active) ; 2s width
p_inStates(4) => s_topUpBeamLostGate(1), -- beam lost gated (1 : window active) ; 2s width
p_inStates(5) => s_linacMPLED(0), -- time between 2 SPM synchro pulses exceeded the maximum delay
p_inStates(6) => s_linacMONdelayError(0), -- time between 2 SPM exceeded the maximum delay
p_inStates(7) => s_linacMONdelayError(1), -- time between 2 LPM exceeded the maximum delay
p_inStates(8) => s_linacMONLED(0), -- simultaneous SPM / LPM
p_inStates(9) => s_freqDivLED(0), -- time between 2 CLK_SR pulses exceeded the maximum delay
p_status => s_status,
p_cfgSW => pin_SW, -- configuration switch (duplication, top-up, etc.)
p_inStates(0) => s_dupLED(0), -- time between 2 synchro pulses exceeded the maximum delay
p_inStates(1) => s_topUpTopUpGate(0), -- top-up gated (1 : window active)
p_inStates(2) => s_topUpBeamLostGate(0), -- beam lost gated (1 : window active)
p_inStates(3) => s_topUpTopUpGate(1), -- top-up gated (1 : window active) ; 2s width
p_inStates(4) => s_topUpBeamLostGate(1), -- beam lost gated (1 : window active) ; 2s width
p_inStates(5) => s_linacMPLED(0), -- time between 2 SPM synchro pulses exceeded the maximum delay
p_inStates(6) => s_linacMONdelayError(0), -- time between 2 SPM exceeded the maximum delay
p_inStates(7) => s_linacMONdelayError(1), -- time between 2 LPM exceeded the maximum delay
p_inStates(8) => s_linacMONLED(0), -- simultaneous SPM / LPM
p_inStates(9) => s_freqDivLED(0), -- time between 2 CLK_SR pulses exceeded the maximum delay
p_inStates(10) => s_linacSYNCLOCKstate, -- interlock state (1 : ON ; 0 : non interlock)
p_status => s_status,
p_cfgSW => pin_SW, -- configuration switch (duplication, top-up, etc.)
-- Other signals
p_clk60MHz => s_clk60MHz, -- clock 60 MHz
p_reset => s_reset -- reset
p_clk60MHz => s_clk60MHz, -- clock 60 MHz
p_reset => s_reset -- reset
);
-- Signal duplication block
......@@ -524,16 +533,28 @@ architecture rtl_top of top is
p_freqDIV_LED => s_freqDivLED
);
-- LINAC synchronized interlock block
linacSynchroLOCK : entity work.linacSYNCLOCK_top (rtl_linacSYNCLOCK_top)
port map (
p_linacSYNCLOCK_inTTL => pin_inTTL(1 downto 0),
p_linacSYNCLOCK_outTTL => s_linacSYNCLOCKOutTTL,
p_linacSYNCLOCK_outPECL => s_linacSYNCLOCKOutPECL,
p_linacSYNCLOCK_clk60MHz => s_clk60MHz,
p_linacSYNCLOCK_reset => s_reset,
p_linacSYNCLOCK_state => s_linacSYNCLOCKstate, -- Status
p_linacSYNCLOCK_LED => s_linacSYNCLOCKLED
);
-- Clock padding block
clkPADDING : entity work.clkPADDING_top (rtl_clkPADDING_top)
port map (
p_clkPADDING_clk500mHz => s_clk500mhz,
p_clkPADDING_clk_mon => pin_inTTL(0),
p_clkPADDING_clk_sr => pin_inTTL(1),
p_clkPADDING_reset => s_reset,
p_clkPADDING_outTTL => s_clkPaddingOutTTL,
p_clkPADDING_outPECL => s_clkPaddingOutPECL,
p_clkPADDING_LED => s_clkPaddingLED
p_clkPADDING_clk500mHz => s_clk500mhz,
p_clkPADDING_clk_mon => pin_inTTL(0),
p_clkPADDING_clk_sr => pin_inTTL(1),
p_clkPADDING_reset => s_reset,
p_clkPADDING_outTTL => s_clkPaddingOutTTL,
p_clkPADDING_outPECL => s_clkPaddingOutPECL,
p_clkPADDING_LED => s_clkPaddingLED
);
-- Test
......@@ -549,35 +570,39 @@ architecture rtl_top of top is
-- Multiplexer
outMux : entity work.outputMux (rtl_outputMux)
port map (
-- Duplication block inputs
-- Duplication block mux inputs
p_dup_outTTL => s_dupOutTTL,
p_dup_outPECL => s_dupOutPECL,
p_dup_LED => s_dupLED,
-- Top-up block inputs
-- Top-up block mux inputs
p_topUp_outTTL => s_topUpOutTTL,
p_topUp_outPECL => s_topUpOutPECL,
p_topUp_LED => s_topUpLED,
-- LINAC multipulses block inputs
-- LINAC multipulses block mux inputs
p_linacMP_outTTL => s_linacMPOutTTL,
p_linacMP_outPECL => s_linacMPOutPECL,
p_linacMP_LED => s_linacMPLED,
-- LINAC monitoring block inputs
-- LINAC monitoring block mux inputs
p_linacMON_outTTL => s_linacMONOutTTL,
p_linacMON_outPECL => s_linacMONOutPECL,
p_linacMON_LED => s_linacMONLED,
-- Test block inputs
-- Test block mux inputs
p_test_outTTL => s_testOutTTL,
p_test_outPECL => s_testOutPECL,
p_test_LED => s_testLED,
-- Frequency divider block inputs
-- Frequency divider block mux inputs
p_freqDIV_outTTL => s_freqDivOutTTL,
p_freqDIV_outPECL => s_freqDivOutPECL,
p_freqDIV_LED => s_freqDivLED,
-- Clock padding block inputs
-- LINAC synchronized interlock block mux inputs
p_linacSYNCLOCK_outTTL => s_linacSYNCLOCKOutTTL,
p_linacSYNCLOCK_outPECL => s_linacSYNCLOCKOutPECL,
p_linacSYNCLOCK_LED => s_linacSYNCLOCKLED,
-- Clock padding block mux inputs
p_clkPADDING_outTTL => s_clkPaddingOutTTL,
p_clkPADDING_outPECL => s_clkPaddingOutPECL,
p_clkPADDING_LED => s_clkPaddingLED,
-- Mux block outputs
-- Mux block mux outputs
p_mux_SWsel => pin_SW,
p_mux_outTTL => pin_outTTL,
p_mux_outPECL => pin_outPECL,
......
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