VHDL : code cleanup

On branch development modified: fpga/TimEX3/TimEX3_eeprom.mcs modified: fpga/sources/registers_init.vhdl modified: fpga/sources/src_cPCI/cPCI_hermes.vhdl modified: fpga/sources/src_cPCI/cPCI_hermes_registers.vhdl modified: fpga/sources/src_cPCI/cPCI_registerMux.vhdl modified: fpga/sources/top.vhdl new file: fpga/sources/type_lib.vhdl

VHDL : code cleanup
On branch development modified: fpga/TimEX3/TimEX3_eeprom.mcs modified: fpga/sources/registers_init.vhdl modified: fpga/sources/src_cPCI/cPCI_hermes.vhdl modified: fpga/sources/src_cPCI/cPCI_hermes_registers.vhdl modified: fpga/sources/src_cPCI/cPCI_registerMux.vhdl modified: fpga/sources/top.vhdl new file: fpga/sources/type_lib.vhdl
28062311 · Jean-Paul Ricaud · 686fe9ce · 28062311 · 28062311 · 28062311
Commit 28062311 authored Dec 09, 2013 by Jean-Paul Ricaud
7 changed files
--- a/fpga/TimEX3/TimEX3_eeprom.mcs
+++ b/fpga/TimEX3/TimEX3_eeprom.mcs
--- a/fpga/sources/registers_init.vhdl
+++ b/fpga/sources/registers_init.vhdl
@@ -9,7 +9,7 @@
 -- File     : registers_init.vhdl
 -- Revision : x.x.x
 -- Created  : March 06, 2013
-- Updated  : November 26, 2013
+-- Updated  : December 05, 2013
 --------------------------------------------------------------------------------
 -- Author       : Jean-Paul Ricaud
 -- Organization : Synchrotron Soleil
@@ -41,6 +41,9 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

+library work;
+use work.type_lib.all;
+
 --------------------------------------------------------------------------------
 --------------------------------------------------------------------------------
 --------------------------------------------------------------------------------
@@ -50,27 +53,38 @@ package registers_init is
  -- Registers init values
  ------------------------------------------------------------------------------
  -- Write registers
-  constant c_test_reg_init    : std_logic_vector (31 downto 0) := X"00000000";
-  constant c_status_reg_init  : std_logic_vector (8 downto 0)  := "000000000";
-  constant c_cmd_reg_init     : std_logic_vector (31 downto 0) := X"00000000";
-  constant c_wRegister0_init  : std_logic_vector (31 downto 0) := X"00000000";
-  constant c_wRegister1_init, c_dupMissingPulseDelay_init      : std_logic_vector (31 downto 0) := X"000493E0";
-  constant c_wRegister2_init, c_beamLostHoldOffMaxDelay_init   : std_logic_vector (31 downto 0) := X"00000000";
-  constant c_wRegister3_init, c_beamLostHoldOnMaxDelay_init    : std_logic_vector (31 downto 0) := X"00000000";
-  constant c_wRegister4_init, c_topUpGateHoldOff_init          : std_logic_vector (31 downto 0) := X"000001F4";
-  constant c_wRegister5_init, c_topUpGateWidth_init            : std_logic_vector (31 downto 0) := X"000001F4";
-  constant c_wRegister6_init  : std_logic_vector (31 downto 0) := X"00000000";
-  constant c_wRegister7_init, c_linacMPMissingPulseDelay_init  : std_logic_vector (31 downto 0) := X"000493E0";
-  constant c_wRegister8_init  : std_logic_vector (31 downto 0) := X"00000000";
-  constant c_wRegister9_init, c_dupMissingSPMDelay_init        : std_logic_vector (31 downto 0) := X"000493E0";
-  constant c_wRegister10_init : std_logic_vector (31 downto 0) := X"00000000";
-  constant c_wRegister11_init, c_dupMissingLPMDelay_init       : std_logic_vector (31 downto 0) := X"000493E0";
-  constant c_wRegister12_init : std_logic_vector (31 downto 0) := X"00000000";
-  constant c_wRegister13_init : std_logic_vector (31 downto 0) := X"00000000";
+  constant c_test_reg_init   : std_logic_vector (31 downto 0) := X"00000000";
+  constant c_status_reg_init : std_logic_vector (8 downto 0)  := "000000000";
+  constant c_cmd_reg_init    : std_logic_vector (31 downto 0) := X"00000000";
+
+  constant c_wRegister_init : register_array := (
+    -- Duplication
+    -- time between 2 pulses (read only), maximum delay before a missing synchro is signaled
+    X"00000000", X"000493E0",
+    -- Top-Up
+    -- beam lost hold off time, beam lost window width, gating hold off time, gating window time
+    X"00000000", X"00000000", X"000001F4", X"000001F4",
+    -- LINAC SPM multipulses
+    -- time between 2 pulses (read only), maximum delay before a missing synchro is signaled
+    X"00000000", X"000493E0",
+    -- LINAC monitoring
+    -- time between 2 SPM pulses (read only), maximum delay before a missing SPM is signaled,
+    -- time between 2 LPM pulses (read only), maximum delay before a missing LPM is signaled,
+    -- number of simultaneous SPM / LPM trigg (read only), reset the s_linacMONsimTrigg register
+    X"00000000", X"000493E0", X"00000000", X"000493E0", X"00000000", X"00000000");
+
+  constant c_dupMissingPulseDelay_init     : std_logic_vector (31 downto 0) := X"000493E0";
+  constant c_beamLostHoldOffMaxDelay_init  : std_logic_vector (31 downto 0) := X"00000000";
+  constant c_beamLostHoldOnMaxDelay_init   : std_logic_vector (31 downto 0) := X"00000000";
+  constant c_topUpGateHoldOff_init         : std_logic_vector (31 downto 0) := X"000001F4";
+  constant c_topUpGateWidth_init           : std_logic_vector (31 downto 0) := X"000001F4";
+  constant c_linacMPMissingPulseDelay_init : std_logic_vector (31 downto 0) := X"000493E0";
+  constant c_dupMissingSPMDelay_init       : std_logic_vector (31 downto 0) := X"000493E0";
+  constant c_dupMissingLPMDelay_init       : std_logic_vector (31 downto 0) := X"000493E0";

  -- Read registers
-  constant c_board_id         : std_logic_vector (31 downto 0) := X"4AC0FA5C"; -- board ID for TimEX3
-  constant c_firmware_rev     : std_logic_vector (31 downto 0) := X"000000A0"; -- firmware's version
+  constant c_board_id     : std_logic_vector (31 downto 0) := X"4AC0FA5C"; -- board ID for TimEX3
+  constant c_firmware_rev : std_logic_vector (31 downto 0) := X"000000A0"; -- firmware's version

 end package registers_init;


--- a/fpga/sources/src_cPCI/cPCI_hermes.vhdl
+++ b/fpga/sources/src_cPCI/cPCI_hermes.vhdl
--- a/fpga/sources/src_cPCI/cPCI_hermes_registers.vhdl
+++ b/fpga/sources/src_cPCI/cPCI_hermes_registers.vhdl
@@ -7,7 +7,7 @@
 -- File     : cPCI_hermes_registers.vhdl
 -- Revision : x.x.x
 -- Created  : October 26, 2012
-- Updated  : November 08, 2013
+-- Updated  : December 04, 2013
 --------------------------------------------------------------------------------
 -- Author       : Jean-Paul Ricaud
 -- Organization : Synchrotron Soleil
@@ -41,6 +41,9 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

+library work;
+use work.type_lib.all;
+
 --------------------------------------------------------------------------------
 --------------------------------------------------------------------------------
 --------------------------------------------------------------------------------
@@ -55,59 +58,64 @@ package cPCI_hermes_registers is
  constant c_add_config_reg   : std_logic_vector (9 downto 2) := "00000011"; -- config register
  constant c_add_status_reg   : std_logic_vector (9 downto 2) := "00000100"; -- status register
  constant c_add_cmd_reg      : std_logic_vector (9 downto 2) := "00000101"; -- commands register
-  constant c_add_register0    : std_logic_vector (9 downto 2) := "00000110"; -- register 0
-  constant c_add_register1    : std_logic_vector (9 downto 2) := "00000111"; -- register 1
-  constant c_add_register2    : std_logic_vector (9 downto 2) := "00001000"; -- register 2
-  constant c_add_register3    : std_logic_vector (9 downto 2) := "00001001"; -- register 3
-  constant c_add_register4    : std_logic_vector (9 downto 2) := "00001010"; -- register 4
-  constant c_add_register5    : std_logic_vector (9 downto 2) := "00001011"; -- register 5
-  constant c_add_register6    : std_logic_vector (9 downto 2) := "00001100"; -- register 6
-  constant c_add_register7    : std_logic_vector (9 downto 2) := "00001101"; -- register 7
-  constant c_add_register8    : std_logic_vector (9 downto 2) := "00001110"; -- register 8
-  constant c_add_register9    : std_logic_vector (9 downto 2) := "00001111"; -- register 9
-  constant c_add_register10   : std_logic_vector (9 downto 2) := "00010000"; -- register 10
-  constant c_add_register11   : std_logic_vector (9 downto 2) := "00010001"; -- register 11
-  constant c_add_register12   : std_logic_vector (9 downto 2) := "00010010"; -- register 12
-  constant c_add_register13   : std_logic_vector (9 downto 2) := "00010011"; -- register 13
  constant c_add_foo_reg      : std_logic_vector (9 downto 2) := "00010100"; -- foo register, not used

+  constant c_add_register : add_register_array := (
+    "00000110",  -- register 0
+    "00000111",  -- register 1
+    "00001000",  -- register 2
+    "00001001",  -- register 3
+    "00001010",  -- register 4
+    "00001011",  -- register 5
+    "00001100",  -- register 6
+    "00001101",  -- register 7
+    "00001110",  -- register 8
+    "00001111",  -- register 9
+    "00010000",  -- register 10
+    "00010001",  -- register 11
+    "00010010",  -- register 12
+    "00010011"); -- register 13
+
  ------------------------------------------------------------------------------
  -- Registers
  ------------------------------------------------------------------------------
-  --Write registers
-  signal s_test_reg    : std_logic_vector (31 downto 0); -- test register
-  signal s_status_reg  : std_logic_vector (31 downto 0); -- status register
-  signal s_cmd_reg     : std_logic_vector (31 downto 0); -- command register ; s_CSW = "000000000000001"
-  signal s_wRegister0  : std_logic_vector (31 downto 0); -- wRegister 0      ; s_CSW = "000000000000010"
-  signal s_wRegister1  : std_logic_vector (31 downto 0); -- wRegister 1      ; s_CSW = "000000000000100"
-  signal s_wRegister2  : std_logic_vector (31 downto 0); -- wRegister 2      ; s_CSW = "000000000001000"
-  signal s_wRegister3  : std_logic_vector (31 downto 0); -- wRegister 3      ; s_CSW = "000000000010000"
-  signal s_wRegister4  : std_logic_vector (31 downto 0); -- wRegister 4      ; s_CSW = "000000000100000"
-  signal s_wRegister5  : std_logic_vector (31 downto 0); -- wRegister 5      ; s_CSW = "000000001000000"
-  signal s_wRegister6  : std_logic_vector (31 downto 0); -- wRegister 6      ; s_CSW = "000000010000000"
-  signal s_wRegister7  : std_logic_vector (31 downto 0); -- wRegister 7      ; s_CSW = "000000100000000"
-  signal s_wRegister8  : std_logic_vector (31 downto 0); -- wRegister 8      ; s_CSW = "000001000000000"
-  signal s_wRegister9  : std_logic_vector (31 downto 0); -- wRegister 9      ; s_CSW = "000010000000000"
-  signal s_wRegister10 : std_logic_vector (31 downto 0); -- wRegister 10     ; s_CSW = "000100000000000"
-  signal s_wRegister11 : std_logic_vector (31 downto 0); -- wRegister 11     ; s_CSW = "001000000000000"
-  signal s_wRegister12 : std_logic_vector (31 downto 0); -- wRegister 12     ; s_CSW = "010000000000000"
-  signal s_wRegister13 : std_logic_vector (31 downto 0); -- wRegister 13     ; s_CSW = "100000000000000"
+  -- Write registers
+  signal s_test_reg   : std_logic_vector (31 downto 0); -- test register
+  signal s_status_reg : std_logic_vector (31 downto 0); -- status register
+  signal s_cmd_reg    : std_logic_vector (31 downto 0); -- command register ; s_CSW = "000000000000001"
+
+  -- wRegister 0  ; s_CSW = "000000000000010"
+  -- wRegister 1  ; s_CSW = "000000000000100"
+  -- wRegister 2  ; s_CSW = "000000000001000"
+  -- wRegister 3  ; s_CSW = "000000000010000"
+  -- wRegister 4  ; s_CSW = "000000000100000"
+  -- wRegister 5  ; s_CSW = "000000001000000"
+  -- wRegister 6  ; s_CSW = "000000010000000"
+  -- wRegister 7  ; s_CSW = "000000100000000"
+  -- wRegister 8  ; s_CSW = "000001000000000"
+  -- wRegister 9  ; s_CSW = "000010000000000"
+  -- wRegister 10 ; s_CSW = "000100000000000"
+  -- wRegister 11 ; s_CSW = "001000000000000"
+  -- wRegister 12 ; s_CSW = "010000000000000"
+  -- wRegister 13 ; s_CSW = "100000000000000"
+  signal s_wRegister : register_array;

-  --Read registers
-  signal s_rRegister0  : std_logic_vector (31 downto 0); -- rRegister 0      ; CSR = "000000000000001"
-  signal s_rRegister1  : std_logic_vector (31 downto 0); -- rRegister 0      ; CSR = "000000000000010"
-  signal s_rRegister2  : std_logic_vector (31 downto 0); -- rRegister 0      ; CSR = "000000000000100"
-  signal s_rRegister3  : std_logic_vector (31 downto 0); -- rRegister 0      ; CSR = "000000000001000"
-  signal s_rRegister4  : std_logic_vector (31 downto 0); -- rRegister 0      ; CSR = "000000000010000"
-  signal s_rRegister5  : std_logic_vector (31 downto 0); -- rRegister 0      ; CSR = "000000000100000"
-  signal s_rRegister6  : std_logic_vector (31 downto 0); -- rRegister 0      ; CSR = "000000001000000"
-  signal s_rRegister7  : std_logic_vector (31 downto 0); -- rRegister 0      ; CSR = "000000010000000"
-  signal s_rRegister8  : std_logic_vector (31 downto 0); -- rRegister 0      ; CSR = "000000100000000"
-  signal s_rRegister9  : std_logic_vector (31 downto 0); -- rRegister 0      ; CSR = "000001000000000"
-  signal s_rRegister10 : std_logic_vector (31 downto 0); -- rRegister 0      ; CSR = "000010000000000"
-  signal s_rRegister11 : std_logic_vector (31 downto 0); -- rRegister 0      ; CSR = "000100000000000"
-  signal s_rRegister12 : std_logic_vector (31 downto 0); -- rRegister 0      ; CSR = "001000000000000"
-  signal s_rRegister13 : std_logic_vector (31 downto 0); -- rRegister 0      ; CSR = "010000000000000"
+  -- Read registers
+  -- rRegister 0  ; CSR = "000000000000001"
+  -- rRegister 1  ; CSR = "000000000000010"
+  -- rRegister 2  ; CSR = "000000000000100"
+  -- rRegister 3  ; CSR = "000000000001000"
+  -- rRegister 4  ; CSR = "000000000010000"
+  -- rRegister 5  ; CSR = "000000000100000"
+  -- rRegister 6  ; CSR = "000000001000000"
+  -- rRegister 7  ; CSR = "000000010000000"
+  -- rRegister 8  ; CSR = "000000100000000"
+  -- rRegister 9  ; CSR = "000001000000000"
+  -- rRegister 10 ; CSR = "000010000000000"
+  -- rRegister 11 ; CSR = "000100000000000"
+  -- rRegister 12 ; CSR = "001000000000000"
+  -- rRegister 13 ; CSR = "010000000000000"
+  signal s_rRegister : register_array;

 end package cPCI_hermes_registers;


--- a/fpga/sources/src_cPCI/cPCI_registerMux.vhdl
+++ b/fpga/sources/src_cPCI/cPCI_registerMux.vhdl
--- a/fpga/sources/top.vhdl
+++ b/fpga/sources/top.vhdl
--- a/fpga/sources/type_lib.vhdl
+++ b/fpga/sources/type_lib.vhdl
+--------------------------------------------------------------------------------
+-- Title   : type library
+-- Project : TimEX3
+--------------------------------------------------------------------------------
+-- Description : type declaration lib
+--------------------------------------------------------------------------------
+-- File     : type_lib.vhdl
+-- Revision : x.x.x
+-- Created  : Decemeber 04, 2013
+-- Updated  : December 06, 2013
+--------------------------------------------------------------------------------
+-- Author       : Jean-Paul Ricaud
+-- Organization : Synchrotron Soleil
+-- Web          : http://www.synchrotron-soleil.fr
+-- Email        : jean-paul.ricaud@synchrotron-soleil.fr
+--------------------------------------------------------------------------------
+-- Copyright (C) 2012 - 2013 Synchrotron Soleil
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU Lesser General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Modifications :
+--
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+package type_lib is
+
+  type register_array is array (0 to 13) of std_logic_vector (31 downto 0);
+  type add_register_array is array (0 to 13) of std_logic_vector (9 downto 2);
+
+end package type_lib;
+
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+package body type_lib is
+
+end package body type_lib;
+