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Commit 4563b9be authored by Jean-Paul Ricaud's avatar Jean-Paul Ricaud
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VHDL : added frequency divider block for slicing synchro DG 

 On branch development

	modified:   fpga/sources/outputmux.vhdl
	modified:   fpga/sources/registers_init.vhdl
	modified:   fpga/sources/src_cPCI/cPCI_registerMux.vhdl
	modified:   fpga/sources/src_cPCI/cPCI_statusManager.vhdl
	modified:   fpga/sources/src_duplication/dup_leds.vhdl
	new file:   fpga/sources/src_freqDIV/freqDIV_clkdiv.vhdl
	new file:   fpga/sources/src_freqDIV/freqDIV_config.txt
	new file:   fpga/sources/src_freqDIV/freqDIV_leds.vhdl
	new file:   fpga/sources/src_freqDIV/freqDIV_monitoring.vhdl
	new file:   fpga/sources/src_freqDIV/freqDIV_top.vhdl
	modified:   fpga/sources/src_linacMON/linacMON_leds.vhdl
	modified:   fpga/sources/src_linacMP/linacMP_leds.vhdl
	modified:   fpga/sources/src_topup/topup_beamlost.vhdl
	modified:   fpga/sources/src_topup/topup_gating.vhdl
	modified:   fpga/sources/top.vhdl
	modified:   fpga/sources/type_lib.vhdl
parent f505d678
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Showing with 784 additions and 120 deletions
fpga/sources/outputmux.vhdl
View file @ 4563b9be
......@@ -5,6 +5,7 @@
-- Description : Output multiplexer
-- SW 5-4-3-2-1-0
-- 1-1-1-1-1-1 : board test
-- 0-0-0-1-0-0 : frequency divider
-- 0-0-0-0-1-1 : LINAC monitoring
-- 0-0-0-0-1-0 : LINAC multipulse
-- 0-0-0-0-0-1 : top-up trigger
......@@ -13,14 +14,14 @@
-- File : outputmux.vhdl
-- Revision : x.x.x
-- Created : October 26, 2012
-- Updated : July 10, 2013
-- Updated : February 03, 2013
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2013 Synchrotron Soleil
-- Copyright (C) 2012 - 2014 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
......@@ -40,6 +41,8 @@
-- Modifications :
-- Version 1.4.0 ; July 09 2013 ; Jean-Paul Ricaud
-- * Added LINAC monitoring function
-- Version 1.6.1 ; February 03 2014 ; Jean-Paul Ricaud
-- * Added frequency divider block for slicing DG
--
--------------------------------------------------------------------------------
......@@ -68,6 +71,10 @@ entity outputMux is
p_linacMON_outTTL : in std_logic_vector (4 downto 0);
p_linacMON_outPECL : in std_logic_vector (4 downto 0);
p_linacMON_LED : in std_logic_vector (1 downto 0);
-- Freaquency divider block
p_freqDIV_outTTL : in std_logic_vector (4 downto 0);
p_freqDIV_outPECL : in std_logic_vector (4 downto 0);
p_freqDIV_LED : in std_logic_vector (1 downto 0);
-- Test block
p_test_outTTL : in std_logic_vector (4 downto 0);
p_test_outPECL : in std_logic_vector (4 downto 0);
......@@ -108,6 +115,7 @@ architecture rtl_outputMux of outputMux is
p_topUp_outTTL when "000001",
p_linacMP_outTTL when "000010",
p_linacMON_outTTL when "000011",
p_freqDIV_outTTL when "000100",
p_test_outTTL when OTHERS;
-- LVPECL ouuputs selection
......@@ -117,6 +125,7 @@ architecture rtl_outputMux of outputMux is
p_topUp_outPECL when "000001",
p_linacMP_outPECL when "000010",
p_linacMON_outPECL when "000011",
p_freqDIV_outPECL when "000100",
p_test_outPECL when OTHERS;
-- LEDs outputs selection
......@@ -126,6 +135,7 @@ architecture rtl_outputMux of outputMux is
p_topUp_LED when "000001",
p_linacMP_LED when "000010",
p_linacMON_LED when "000011",
p_freqDIV_LED when "000100",
p_test_LED when OTHERS;
------------------------------------------------------------------------------
......
fpga/sources/registers_init.vhdl
View file @ 4563b9be
......@@ -9,14 +9,14 @@
-- File : registers_init.vhdl
-- Revision : x.x.x
-- Created : March 06, 2013
-- Updated : December 05, 2013
-- Updated : February 03, 2014
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2013 Synchrotron Soleil
-- Copyright (C) 2012 - 2014 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
......@@ -54,37 +54,31 @@ package registers_init is
------------------------------------------------------------------------------
-- Write registers
constant c_test_reg_init : std_logic_vector (31 downto 0) := X"00000000";
constant c_status_reg_init : std_logic_vector (8 downto 0) := "000000000";
constant c_status_reg_init : std_logic_vector (9 downto 0) := "0000000000";
constant c_cmd_reg_init : std_logic_vector (31 downto 0) := X"00000000";
constant c_wRegister_init : register_array := (
-- Duplication
-- *** Duplication ***
-- time between 2 pulses (read only), maximum delay before a missing synchro is signaled
X"00000000", X"000493E0",
-- Top-Up
-- beam lost hold off time, beam lost window width, gating hold off time, gating window time
-- *** Top-Up ***
-- beam lost hold off time, beam lost hold on width, gating hold off time, gating window time
X"00000000", X"00000000", X"000001F4", X"000001F4",
-- LINAC SPM multipulses
-- *** LINAC SPM multipulses ***
-- time between 2 pulses (read only), maximum delay before a missing synchro is signaled
X"00000000", X"000493E0",
-- LINAC monitoring
-- *** LINAC monitoring ***
-- time between 2 SPM pulses (read only), maximum delay before a missing SPM is signaled,
-- time between 2 LPM pulses (read only), maximum delay before a missing LPM is signaled,
-- number of simultaneous SPM / LPM trigg (read only), reset the s_linacMONsimTrigg register
X"00000000", X"000493E0", X"00000000", X"000493E0", X"00000000", X"00000000");
constant c_dupMissingPulseDelay_init : std_logic_vector (31 downto 0) := X"000493E0";
constant c_beamLostHoldOffMaxDelay_init : std_logic_vector (31 downto 0) := X"00000000";
constant c_beamLostHoldOnMaxDelay_init : std_logic_vector (31 downto 0) := X"00000000";
constant c_topUpGateHoldOff_init : std_logic_vector (31 downto 0) := X"000001F4";
constant c_topUpGateWidth_init : std_logic_vector (31 downto 0) := X"000001F4";
constant c_linacMPMissingPulseDelay_init : std_logic_vector (31 downto 0) := X"000493E0";
constant c_dupMissingSPMDelay_init : std_logic_vector (31 downto 0) := X"000493E0";
constant c_dupMissingLPMDelay_init : std_logic_vector (31 downto 0) := X"000493E0";
X"00000000", X"000493E0", X"00000000", X"000493E0", X"00000000", X"00000000",
-- *** Frequency divider ***
-- time between 2 CLK_SR (read only), maximum delay before a missing CLK_SR is signaled
X"00000000", X"000493E0");
-- Read registers
constant c_board_id : std_logic_vector (31 downto 0) := X"4AC0FA5C"; -- board ID for TimEX3
constant c_firmware_rev : std_logic_vector (31 downto 0) := X"000000A0"; -- firmware's version
constant c_firmware_rev : std_logic_vector (31 downto 0) := X"000000A1"; -- firmware's version
end package registers_init;
......
fpga/sources/src_cPCI/cPCI_registerMux.vhdl
View file @ 4563b9be
......@@ -5,6 +5,7 @@
-- Description : Register multiplexer
-- SW 5-4-3-2-1-0
-- 1-1-1-1-1-1 : board test
-- 0-0-0-1-0-0 : frequency duplication
-- 0-0-0-0-1-1 : LINAC monitoring
-- 0-0-0-0-1-0 : LINAC multipulse
-- 0-0-0-0-0-1 : top-up trigger
......@@ -13,14 +14,14 @@
-- File : cPCI_registerMux.vhdl
-- Revision : x.x.x
-- Created : November 17, 2013
-- Updated : December 05, 2013
-- Updated : Ferbuary 03, 2014
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2013 Synchrotron Soleil
-- Copyright (C) 2012 - 2014 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
......@@ -66,8 +67,8 @@ entity cPCI_registerMux is
p_mux_csw : in std_logic_vector (15 downto 0); -- chip select of internal write transfert
p_mux_csr : in std_logic_vector (15 downto 0); -- chip select of internal read transfert
p_csw : out std_logic_vector (15 downto 0);
p_csr : out std_logic_vector (15 downto 0);
p_csw : out std_logic_vector (20 downto 0);
p_csr : out std_logic_vector (20 downto 0);
-- Congig pin
p_mux_SWsel : in std_logic_vector (5 downto 0)
......@@ -100,7 +101,6 @@ architecture rtl_cPCI_registerMux of cPCI_registerMux is
p_mux_wRegister(0) <=
p_wRegister(0) when "000000",
X"00000000" when OTHERS;
with p_mux_SWsel select
p_mux_wRegister(1) <=
p_wRegister(1) when "000000",
......@@ -111,7 +111,6 @@ architecture rtl_cPCI_registerMux of cPCI_registerMux is
p_mux_wRegister(2) <=
p_wRegister(0) when "000001",
X"00000000" when OTHERS;
with p_mux_SWsel select
p_mux_wRegister(3) <=
p_wRegister(1) when "000001",
......@@ -121,7 +120,6 @@ architecture rtl_cPCI_registerMux of cPCI_registerMux is
p_mux_wRegister(4) <=
p_wRegister(2) when "000001",
X"00000000" when OTHERS;
with p_mux_SWsel select
p_mux_wRegister(5) <=
p_wRegister(3) when "000001",
......@@ -132,7 +130,6 @@ architecture rtl_cPCI_registerMux of cPCI_registerMux is
p_mux_wRegister(6) <=
p_wRegister(0) when "000010",
X"00000000" when OTHERS;
with p_mux_SWsel select
p_mux_wRegister(7) <=
p_wRegister(1) when "000010",
......@@ -143,51 +140,58 @@ architecture rtl_cPCI_registerMux of cPCI_registerMux is
p_mux_wRegister(8) <=
p_wRegister(0) when "000011",
X"00000000" when OTHERS;
with p_mux_SWsel select
p_mux_wRegister(9) <=
p_wRegister(1) when "000011",
X"00000000" when OTHERS;
with p_mux_SWsel select
p_mux_wRegister(10) <=
p_wRegister(2) when "000011",
X"00000000" when OTHERS;
with p_mux_SWsel select
p_mux_wRegister(11) <=
p_wRegister(3) when "000011",
X"00000000" when OTHERS;
with p_mux_SWsel select
p_mux_wRegister(12) <=
p_wRegister(4) when "000011",
X"00000000" when OTHERS;
with p_mux_SWsel select
p_mux_wRegister(13) <=
p_wRegister(5) when "000011",
X"00000000" when OTHERS;
-- Frequency divider write
with p_mux_SWsel select
p_mux_wRegister(14) <=
p_wRegister(0) when "000100",
X"00000000" when OTHERS;
with p_mux_SWsel select
p_mux_wRegister(15) <=
p_wRegister(1) when "000100",
X"00000000" when OTHERS;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Write registers init values mux
with p_mux_SWsel select
p_wRegister_init(0) <=
c_wRegister_init(0) when "000000",
c_wRegister_init(2) when "000001",
c_wRegister_init(6) when "000010",
c_wRegister_init(8) when "000011",
c_wRegister_init(0) when "000000",
c_wRegister_init(2) when "000001",
c_wRegister_init(6) when "000010",
c_wRegister_init(8) when "000011",
c_wRegister_init(14) when "000100",
X"00000000" when OTHERS;
with p_mux_SWsel select
p_wRegister_init(1) <=
c_wRegister_init(1) when "000000",
c_wRegister_init(3) when "000001",
c_wRegister_init(7) when "000010",
c_wRegister_init(9) when "000011",
X"00000000" when OTHERS;
c_wRegister_init(1) when "000000",
c_wRegister_init(3) when "000001",
c_wRegister_init(7) when "000010",
c_wRegister_init(9) when "000011",
c_wRegister_init(15) when "000100",
X"00000000" when OTHERS;
with p_mux_SWsel select
p_wRegister_init(2) <=
......@@ -226,18 +230,20 @@ architecture rtl_cPCI_registerMux of cPCI_registerMux is
-- Read mux
with p_mux_SWsel select
p_rRegister(0) <=
p_mux_rRegister(0) when "000000",
p_mux_rRegister(2) when "000001",
p_mux_rRegister(6) when "000010",
p_mux_rRegister(8) when "000011",
p_mux_rRegister(0) when "000000",
p_mux_rRegister(2) when "000001",
p_mux_rRegister(6) when "000010",
p_mux_rRegister(8) when "000011",
p_mux_rRegister(14) when "000100",
X"00000000" when OTHERS;
with p_mux_SWsel select
p_rRegister(1) <=
p_mux_rRegister(1) when "000000",
p_mux_rRegister(3) when "000001",
p_mux_rRegister(7) when "000010",
p_mux_rRegister(9) when "000011",
p_mux_rRegister(1) when "000000",
p_mux_rRegister(3) when "000001",
p_mux_rRegister(7) when "000010",
p_mux_rRegister(9) when "000011",
p_mux_rRegister(15) when "000100",
X"00000000" when OTHERS;
with p_mux_SWsel select
......@@ -281,7 +287,6 @@ architecture rtl_cPCI_registerMux of cPCI_registerMux is
p_csw(1) <=
p_mux_csw(1) when "000000",
'0' when OTHERS;
with p_mux_SWsel select
p_csw(2) <=
p_mux_csw(2) when "000000",
......@@ -292,17 +297,14 @@ architecture rtl_cPCI_registerMux of cPCI_registerMux is
p_csw(3) <=
p_mux_csw(1) when "000001",
'0' when OTHERS;
with p_mux_SWsel select
p_csw(4) <=
p_mux_csw(2) when "000001",
'0' when OTHERS;
with p_mux_SWsel select
p_csw(5) <=
p_mux_csw(3) when "000001",
'0' when OTHERS;
with p_mux_SWsel select
p_csw(6) <=
p_mux_csw(4) when "000001",
......@@ -313,7 +315,6 @@ architecture rtl_cPCI_registerMux of cPCI_registerMux is
p_csw(7) <=
p_mux_csw(1) when "000010",
'0' when OTHERS;
with p_mux_SWsel select
p_csw(8) <=
p_mux_csw(2) when "000010",
......@@ -324,33 +325,38 @@ architecture rtl_cPCI_registerMux of cPCI_registerMux is
p_csw(9) <=
p_mux_csw(1) when "000011",
'0' when OTHERS;
with p_mux_SWsel select
p_csw(10) <=
p_mux_csw(2) when "000011",
'0' when OTHERS;
with p_mux_SWsel select
p_csw(11) <=
p_mux_csw(3) when "000011",
'0' when OTHERS;
with p_mux_SWsel select
p_csw(12) <=
p_mux_csw(4) when "000011",
'0' when OTHERS;
with p_mux_SWsel select
p_csw(13) <=
p_mux_csw(5) when "000011",
'0' when OTHERS;
with p_mux_SWsel select
p_csw(14) <=
p_mux_csw(6) when "000011",
'0' when OTHERS;
p_csw(15) <= p_mux_csw(15);
-- Frequency dividor write strobe mux
with p_mux_SWsel select
p_csw(15) <=
p_mux_csw(1) when "000100",
'0' when OTHERS;
with p_mux_SWsel select
p_csw(16) <=
p_mux_csw(2) when "000100",
'0' when OTHERS;
p_csw(20 downto 17) <= (OTHERS => '0');
------------------------------------------------------------------------------
------------------------------------------------------------------------------
......@@ -371,6 +377,8 @@ architecture rtl_cPCI_registerMux of cPCI_registerMux is
p_csr(14) <= p_mux_csr(14);
p_csr(15) <= p_mux_csr(15);
p_csr (20 downto 16) <= "00000";
------------------------------------------------------------------------------
------------------------------------------------------------------------------
......
fpga/sources/src_cPCI/cPCI_statusManager.vhdl
View file @ 4563b9be
......@@ -9,14 +9,14 @@
-- File : cPCI_statusManager.vhdl
-- Revision : x.x.x
-- Created : December 05, 2012
-- Updated : November 28, 2013
-- Updated : February 03, 2014
-------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
-------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2013 Synchrotron Soleil
-- Copyright (C) 2012 - 2014 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
......@@ -49,7 +49,7 @@ use work.registers_init.all;
-------------------------------------------------------------------------------
entity cPCI_statusManager is
port (
p_inStates : in std_logic_vector (8 downto 0);
p_inStates : in std_logic_vector (9 downto 0);
p_status : out std_logic_vector (29 downto 0);
p_cfgSW : in std_logic_vector (5 downto 0);
p_clk60MHz : in std_logic;
......@@ -68,7 +68,7 @@ architecture rtl_cPCI_statusManager of cPCI_statusManager is
-----------------------------------------------------------------------------
-- signal
-----------------------------------------------------------------------------
signal s_status : std_logic_vector (8 downto 0);
signal s_status : std_logic_vector (9 downto 0);
-----------------------------------------------------------------------------
-- Components
......@@ -85,18 +85,19 @@ architecture rtl_cPCI_statusManager of cPCI_statusManager is
s_status <= c_status_reg_init;
elsif (falling_edge(p_clk60MHz)) then
case p_cfgSW is
when "000000" => s_status <= "00000000" & p_inStates(0);
when "000001" => s_status <= "00000" & p_inStates(4 downto 1);
when "000010" => s_status <= "00000000" & p_inStates(5);
when "000011" => s_status <= "000000" & p_inStates(8 downto 6);
when others => s_status <= "000000000";
when "000000" => s_status <= "000000000" & p_inStates(0);
when "000001" => s_status <= "000000" & p_inStates(4 downto 1);
when "000010" => s_status <= "000000000" & p_inStates(5);
when "000011" => s_status <= "0000000" & p_inStates(8 downto 6);
when "000100" => s_status <= "000000000" & p_inStates(9);
when others => s_status <= "0000000000";
end case;
end if;
end process;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
p_status <= "000000000000000000000" & s_status;
p_status <= "00000000000000000000" & s_status;
end architecture rtl_cPCI_statusManager;
fpga/sources/src_duplication/dup_leds.vhdl
View file @ 4563b9be
......@@ -17,14 +17,14 @@
-- File : dup_leds.vhdl
-- Revision : x.x.x
-- Created : November 07, 2012
-- Updated : November 29, 2013
-- Updated : February 03, 2013
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2013 Synchrotron Soleil
-- Copyright (C) 2012 - 2014 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
......@@ -174,7 +174,7 @@ architecture rtl_dup_leds of dup_leds is
process (p_reset, p_clk60MHz)
begin
if (p_reset = '1') then
s_cnt2max <= unsigned (c_dupMissingPulseDelay_init);
s_cnt2max <= unsigned (c_wRegister_init(1));
s_rstCNT <= '0';
elsif (rising_edge(p_clk60MHz)) then
if (p_csw = '1') then
......
fpga/sources/src_freqDIV/freqDIV_clkdiv.vhdl 0 → 100755
View file @ 4563b9be
--------------------------------------------------------------------------------
-- Title : frequency division block
-- Project : TimEX3
--------------------------------------------------------------------------------
-- Description : frequency division for DG slicing
-- Fout = 1000.7558192399 Hz = CLK_SR / 846 = slicing laser freq
--------------------------------------------------------------------------------
-- File : freqDIV_clkdiv.vhd
-- Revision : x.x.x
-- Created : February 03, 2014
-- Updated : February 03, 2014
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2014 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Modifications :
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
--------------------------------- ENTITY ---------------------------------------
--------------------------------------------------------------------------------
entity freqDIV_clkdiv is
port (
p_clkSR : in std_logic; -- clk input
p_reset : in std_logic; -- reset input
p_clkOUT : out std_logic_vector (4 downto 0); -- clk outputs
p_outPECL : out std_logic_vector (4 downto 0) -- LVPECL outputs
);
end freqDIV_clkdiv;
--------------------------------------------------------------------------------
------------------------------- ARCHITECTURE -----------------------------------
--------------------------------------------------------------------------------
architecture rtl_freqDIV_clkdiv of freqDIV_clkdiv is
------------------------------------------------------------------------------
-- constant
------------------------------------------------------------------------------
constant c_lfsr : std_logic_vector (8 downto 0) := "111100011";
------------------------------------------------------------------------------
-- signal
------------------------------------------------------------------------------
signal s_lfsr : std_logic_vector (8 downto 0);
signal s_lfsr_lsb : std_logic;
signal s_div_423 : std_logic;
signal s_div_846 : std_logic;
------------------------------------------------------------------------------
--------------------------------- Main ---------------------------------------
------------------------------------------------------------------------------
begin
-- s_div_423 = 2001.5116384798 Hz = CLK_SR / 423
process (p_clkSR, p_reset)
begin
if (p_reset = '1') then
s_lfsr <= (OTHERS => '0');
s_div_423 <= '0';
elsif (rising_edge(p_clkSR)) then
if(s_lfsr = c_lfsr) then
s_lfsr <= (OTHERS => '0');
s_div_423 <= '1';
else
s_lfsr <= s_lfsr(7 downto 0) & s_lfsr_lsb;
s_div_423 <= '0';
end if;
end if;
end process;
-- s_div_846 = s_div_423 / 2 = 1000.7558192399 Hz = CLK_SR / 846
process (p_reset, s_div_423)
begin
if (p_reset = '1') then
s_div_846 <= '0';
elsif (rising_edge(s_div_423)) then
s_div_846 <= not s_div_846;
end if;
end process;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
s_lfsr_lsb <= s_lfsr(8) xnor s_lfsr(4);
p_clkOUT(1) <= s_div_846;
p_clkOUT(2) <= s_div_846;
p_clkOUT(3) <= s_div_846;
p_clkOUT(4) <= s_div_846;
-- Unused signals
p_clkOUT(0) <= '0'; -- the IO is used as input
p_outPECL <= "00000";
end rtl_freqDIV_clkdiv;
fpga/sources/src_freqDIV/freqDIV_config.txt 0 → 100755
View file @ 4563b9be
------------------------------------------------------------------------------
-- Title : Configuration of TimEX3
-- Project : TimEX3
-------------------------------------------------------------------------------
-- Description : Differents configuration of the TimEX3
-------------------------------------------------------------------------------
-- File : freqDIV_config.txt
-- Revision : x.x.x
-- Created : February 03, 2014
-- Updated : February 03, 2014
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2014 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Modifications :
--
--------------------------------------------------------------------------------
===============================================================================
Configuration : duplication 1 input to 4 outputs
SW : 5-4-3-2-1-0
0-0-0-1-0-0
IO0 : input - input signal
IO1 : output - duplicated signal
IO2 : output - duplicated signal
IO3 : output - duplicated signal
IO4 : output - duplicated signal
Green LED on = OK
Red LED on = missing trigger on the input
R3, R28, R29, R30, R31 => Qty = 1
R6, R16, R17, R18, R19 => Qty = 0
===============================================================================
fpga/sources/src_freqDIV/freqDIV_leds.vhdl 0 → 100755
View file @ 4563b9be
--------------------------------------------------------------------------------
-- Title : Leds
-- Project : TimEX3
--------------------------------------------------------------------------------
-- Description : Leds management
--
-- | OFF | ON | BLINKING
-- ======|=====================|=====================|=====================
-- GREEN | FPGA not configured | OK | synchro pulse
-- | | | detected
-- ======|=====================|=====================|=====================
-- RED | OK | no synchro pulse |
-- | | for more than n mn |
-- ======|=====================|=====================|=====================
--
--------------------------------------------------------------------------------
-- File : freqDIV_leds.vhdl
-- Revision : x.x.x
-- Created : February 03, 2014
-- Updated : February 03, 2014
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2014 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Modifications :
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.registers_init.all;
--------------------------------------------------------------------------------
--------------------------------- ENTITY ---------------------------------------
--------------------------------------------------------------------------------
entity freqDIV_leds is
port (
p_inTTL : in std_logic; -- input TTL
p_clk1kHz : in std_logic;
p_clk500mHz : in std_logic;
p_clk60MHz : in std_logic;
p_missingPulseDelay : in std_logic_vector (31 downto 0);
p_csw : in std_logic;
p_reset : in std_logic;
p_led : out std_logic_vector (1 downto 0)
);
end entity freqDIV_leds;
--------------------------------------------------------------------------------
------------------------------- ARCHITECTURE -----------------------------------
--------------------------------------------------------------------------------
architecture rtl_freqDIV_leds of freqDIV_leds is
------------------------------------------------------------------------------
-- constant
------------------------------------------------------------------------------
constant s_cnt1max : unsigned (3 downto 0) := "1011"; -- 5s
------------------------------------------------------------------------------
-- signal
------------------------------------------------------------------------------
signal s_cnt1 : unsigned (3 downto 0); -- counter
signal s_cnt2 : unsigned (31 downto 0); -- counter
signal s_cnt2max : unsigned (31 downto 0); -- max delay
signal s_greenLedON : std_logic;
signal s_blink : std_logic;
signal s_rstCNT : std_logic; -- reset the conter after a software delay update
signal s_start : std_logic;
signal s_stop : std_logic;
signal s_hold1 : std_logic;
signal s_hold2 : std_logic;
------------------------------------------------------------------------------
--------------------------------- Main ---------------------------------------
------------------------------------------------------------------------------
begin
-- Green LED
-- The green LED is blinked for 5s after a reset or after a input pulse is
-- dtected. It remains ON in other cases.
process (p_reset, p_inTTL, p_clk500mHz)
begin
if ((p_inTTL = '1') or (p_reset = '1')) then
s_cnt1 <= (OTHERS => '0');
s_greenLedON <= '1'; -- green LED ON
s_blink <= '1'; -- blink the green LED
elsif (rising_edge(p_clk500mHz)) then
if (s_blink = '1') then
if (s_cnt1 < s_cnt1max) then
s_cnt1 <= s_cnt1 + 1;
s_greenLedON <= not s_greenLedON; -- blink the green LED
s_blink <= '1'; -- keep blinking
else
s_cnt1 <= s_cnt1; -- keep the max value
s_greenLedON <= '1'; -- green LED ON
s_blink <= '0'; -- stop blinking
end if;
else
s_cnt1 <= s_cnt1; -- keep the max value
s_greenLedON <= '1'; -- green LED ON
s_blink <= '0'; -- stop blinking
end if;
end if;
end process;
-- Red LED
-- The red LED is off after a reset. It gos ON if no input signal is detected
-- after n mn.
process (p_reset, p_inTTL, s_stop)
begin
if ((s_stop = '1') or (p_reset = '1')) then
s_start <= '0';
elsif (rising_edge(p_inTTL)) then
s_start <= '1';
end if;
end process;
process (p_reset, s_start, p_clk1kHz)
begin
if ((s_start = '0') or (p_reset = '1')) then
s_hold1 <= '0';
s_hold2 <= '0';
s_stop <= '0';
elsif (falling_edge(p_clk1kHz)) then
s_hold1 <= '1';
s_hold2 <= s_hold1;
s_stop <= s_hold2;
end if;
end process;
process (p_reset, s_stop, s_rstCNT, p_clk1kHz)
begin
if ((s_stop = '1') or (p_reset = '1') or (s_rstCNT = '1')) then
s_cnt2 <= (OTHERS => '0');
p_led(0) <= '0'; -- red LED OFF
elsif (rising_edge(p_clk1kHz)) then
if (s_cnt2 < s_cnt2max) then
s_cnt2 <= s_cnt2 + 1;
p_led(0) <= '0'; -- red LED OFF
else
s_cnt2 <= s_cnt2; -- keep the max value in case of overflow
p_led(0) <= '1'; -- red LED ON
end if;
end if;
end process;
-- Latch from the register the maximum delay before a missing synchro pulse
-- is signaled
process (p_reset, p_clk60MHz)
begin
if (p_reset = '1') then
s_cnt2max <= unsigned (c_wRegister_init(15));
s_rstCNT <= '0';
elsif (rising_edge(p_clk60MHz)) then
if (p_csw = '1') then
s_cnt2max <= unsigned (p_missingPulseDelay);
s_rstCNT <= '1';
else
s_cnt2max <= s_cnt2max;
s_rstCNT <= '0';
end if;
end if;
end process;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
p_led(1) <= s_greenLedON;
end architecture rtl_freqDIV_leds;
fpga/sources/src_freqDIV/freqDIV_monitoring.vhdl 0 → 100755
View file @ 4563b9be
--------------------------------------------------------------------------------
-- Title : Monitoring of CLK_SR input
-- Project : TimEX3
--------------------------------------------------------------------------------
-- Description : The CLK_SR signal is monotored at a frequency of 1kHz.
-- A 32 bits conter is used to save the time between two synchroization
-- pulses.
--------------------------------------------------------------------------------
-- File : freqDIV_monitoring.vhdl
-- Revision : x.x.x
-- Created : February 03, 2014
-- Updated : February 03, 2014
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2014 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Modifications :
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
--------------------------------- ENTITY ---------------------------------------
--------------------------------------------------------------------------------
entity freqDIV_monitoring is
port (
p_inTTL : in std_logic; -- TTL input
p_clk1kHz : in std_logic;
p_reset : in std_logic;
p_monitor : out std_logic_vector (31 downto 0) -- register with the time
-- value between two pulses
);
end freqDIV_monitoring;
--------------------------------------------------------------------------------
------------------------------- ARCHITECTURE -----------------------------------
--------------------------------------------------------------------------------
architecture rtl_freqDIV_monitoring of freqDIV_monitoring is
------------------------------------------------------------------------------
-- constant
------------------------------------------------------------------------------
constant s_cntmax : unsigned (31 downto 0) := X"FFFFFFFF";
------------------------------------------------------------------------------
-- signal
------------------------------------------------------------------------------
signal s_cnt : unsigned (31 downto 0); -- counter
signal s_start : std_logic;
signal s_stop : std_logic;
signal s_hold1 : std_logic;
signal s_hold2 : std_logic;
------------------------------------------------------------------------------
--------------------------------- Main ---------------------------------------
------------------------------------------------------------------------------
begin
process (p_reset, p_inTTL, s_stop)
begin
if ((s_stop = '1') or (p_reset = '1')) then
s_start <= '0';
elsif (rising_edge(p_inTTL)) then
s_start <= '1';
end if;
end process;
process (p_reset, s_start, p_clk1kHz)
begin
if ((s_start = '0') or (p_reset = '1')) then
s_hold1 <= '0';
s_hold2 <= '0';
s_stop <= '0';
elsif (falling_edge(p_clk1kHz)) then
s_hold1 <= '1';
s_hold2 <= s_hold1;
s_stop <= s_hold2;
end if;
end process;
process (p_reset, s_stop, p_clk1kHz)
begin
if ((s_stop = '1') or (p_reset = '1')) then
s_cnt <= (OTHERS => '0');
elsif (falling_edge(p_clk1kHz)) then
if (s_cnt < s_cntmax) then
s_cnt <= s_cnt + 1;
else
s_cnt <= s_cnt; -- keep the max value in case of overflow
end if;
end if;
end process;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
p_monitor <= std_logic_vector(s_cnt);
end rtl_freqDIV_monitoring;
fpga/sources/src_freqDIV/freqDIV_top.vhdl 0 → 100755
View file @ 4563b9be
--------------------------------------------------------------------------------
-- Title : Top - frequency division function
-- Project : TimEX3
--------------------------------------------------------------------------------
-- Description : Top sheet of the frequency division block
-- inTTL(0) is the CLK_SR provided by a LOCAL borad. This clk is dided by 846
-- outTTL are CLK_SR / 846
--------------------------------------------------------------------------------
-- File : freqDIV_top.vhdl
-- Revision : x.x.x
-- Created : February 03, 2014
-- Updated : February 03, 2014
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2014 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the Lesser GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Modifications :
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
--------------------------------- ENTITY ---------------------------------------
--------------------------------------------------------------------------------
entity freqDiv_top is
port (
p_freqDIV_inTTL : in std_logic; -- input TTL
p_freqDIV_outTTL : out std_logic_vector (4 downto 0); -- TTL outputs
p_freqDIV_outPECL : out std_logic_vector (4 downto 0); -- LVPECL outputs
p_freqDIV_clk1kHz : in std_logic;
p_freqDIV_clk500mHz : in std_logic;
p_freqDIV_clk60MHz : in std_logic;
p_freqDIV_missingPulseDelay : in std_logic_vector (31 downto 0);
p_freqDIV_csw : in std_logic;
p_freqDIV_reset : in std_logic;
p_freqDIV_pulseMon : out std_logic_vector (31 downto 0); -- pulses monitor
p_freqDIV_led : out std_logic_vector (1 downto 0)
);
end entity freqDiv_top;
--------------------------------------------------------------------------------
------------------------------- ARCHITECTURE -----------------------------------
--------------------------------------------------------------------------------
architecture rtl_freqDiv_top of freqDiv_top is
------------------------------------------------------------------------------
-- constant
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- signal
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--------------------------------- Main ---------------------------------------
------------------------------------------------------------------------------
begin
-- Frequency divider : Fout = 1000.7558192399 Hz = CLK_SR / 846 = slicing laser freq
slicingFreq : entity work.freqDIV_clkdiv (rtl_freqDIV_clkdiv)
port map (
p_clkSR => p_freqDIV_inTTL, -- TTL in
p_reset => p_freqDIV_reset, -- reset
p_clkOUT => p_freqDIV_outTTL, -- TTL out
p_outPECL => p_freqDIV_outPECL -- LVPECL out
);
-- Signal monitoring block
-- The time betwwen 2 input pulses in stored in MONITOR register (in ms)
pulseMonitor : entity work.freqDIV_monitoring (rtl_freqDIV_monitoring)
port map (
p_inTTL => p_freqDIV_inTTL, -- TTL input
p_clk1kHz => p_freqDIV_clk1kHz,
p_reset => p_freqDIV_reset,
p_monitor => p_freqDIV_pulseMon -- register with the time value between two pulses
);
-- LEDs management for the duplication block
-- The green LED is blinked for 5s after a reset or after a input pulse is
-- dtected. It remains ON in other cases.
-- The red LED is off after a reset. It gos ON if no input signal is detected
-- after delay defined in the missingPulseDelay register.
leds : entity work.freqDIV_leds (rtl_freqDIV_leds)
port map (
p_inTTL => p_freqDIV_inTTL, -- TTL input
p_clk1kHz => p_freqDIV_clk1kHz,
p_clk500mHz => p_freqDIV_clk500mHz,
p_clk60MHz => p_freqDIV_clk60MHz,
p_missingPulseDelay => p_freqDIV_missingPulseDelay,
p_csw => p_freqDIV_csw,
p_reset => p_freqDIV_reset,
p_led => p_freqDIV_led
);
------------------------------------------------------------------------------
------------------------------------------------------------------------------
end architecture rtl_freqDiv_top;
fpga/sources/src_linacMON/linacMON_leds.vhdl
View file @ 4563b9be
......@@ -17,14 +17,14 @@
-- File : linacMON_leds.vhdl
-- Revision : x.x.x
-- Created : July 09, 2013
-- Updated : November 29, 2013
-- Updated : February 03, 2014
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2013 Synchrotron Soleil
-- Copyright (C) 2012 - 2014 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
......@@ -220,7 +220,7 @@ architecture rtl_linacMON_leds of linacMON_leds is
process (p_reset, p_clk60MHz)
begin
if (p_reset = '1') then
s_cnt2max <= unsigned (c_dupMissingSPMDelay_init);
s_cnt2max <= unsigned (c_wRegister_init(9));
s_rstCNT2 <= '0';
elsif (rising_edge(p_clk60MHz)) then
if (p_csw(0) = '1') then
......@@ -238,7 +238,7 @@ architecture rtl_linacMON_leds of linacMON_leds is
process (p_reset, p_clk60MHz)
begin
if (p_reset = '1') then
s_cnt3max <= unsigned (c_dupMissingLPMDelay_init);
s_cnt3max <= unsigned (c_wRegister_init(11));
s_rstCNT3 <= '0';
elsif (rising_edge(p_clk60MHz)) then
if (p_csw(1) = '1') then
......
fpga/sources/src_linacMP/linacMP_leds.vhdl
View file @ 4563b9be
......@@ -17,14 +17,14 @@
-- File : linacMP_leds.vhdl
-- Revision : x.x.x
-- Created : March 14, 2013
-- Updated : November 29, 2013
-- Updated : February 03, 2014
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2013 Synchrotron Soleil
-- Copyright (C) 2012 - 2014 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
......@@ -174,7 +174,7 @@ architecture rtl_linacMP_leds of linacMP_leds is
process (p_reset, p_clk60MHz)
begin
if (p_reset = '1') then
s_cnt2max <= unsigned (c_dupMissingPulseDelay_init);
s_cnt2max <= unsigned (c_wRegister_init(7));
s_rstCNT <= '0';
elsif (rising_edge(p_clk60MHz)) then
if (p_csw = '1') then
......
fpga/sources/src_topup/topup_beamlost.vhdl
View file @ 4563b9be
......@@ -168,7 +168,7 @@ architecture rtl_topup_beamlost of topup_beamlost is
process (p_reset, p_clk1kHz, s_rstCNT)
begin
if ((p_reset = '1') or (s_rstCNT = '1')) then
s_cntHoldOn <= unsigned (c_beamLostHoldOnMaxDelay_init);
s_cntHoldOn <= unsigned (c_wRegister_init(3));
s_gateStop <= '0'; -- Beam lost gate (hold on time)
elsif (rising_edge(p_clk1kHz)) then
if (s_gateStart = '1') then
......@@ -184,12 +184,12 @@ architecture rtl_topup_beamlost of topup_beamlost is
end if;
end process;
-- Latch from the register the maximum delay before a missing beam is
-- takes into account
-- Latch from the register the delay before a missing beam is
-- took into account ; beam lost hold off
process (p_reset, p_clk60MHz)
begin
if (p_reset = '1') then
s_holdOffMax <= unsigned (c_beamLostHoldOffMaxDelay_init);
s_holdOffMax <= unsigned (c_wRegister_init(2));
s_rstCNT0 <= '0';
elsif (rising_edge(p_clk60MHz)) then
if (p_csw(0) = '1') then
......@@ -202,12 +202,12 @@ architecture rtl_topup_beamlost of topup_beamlost is
end if;
end process;
-- Latch from the register the maximum delay after a injection is
-- takes into account
-- Latch from the register the hold on delay after an injection
-- Beam lost hold on
process (p_reset, p_clk60MHz)
begin
if (p_reset = '1') then
s_holdOnMax <= unsigned (c_beamLostHoldOnMaxDelay_init);
s_holdOnMax <= unsigned (c_wRegister_init(3));
s_rstCNT1 <= '0';
elsif (rising_edge(p_clk60MHz)) then
if (p_csw(1) = '1') then
......
fpga/sources/src_topup/topup_gating.vhdl
View file @ 4563b9be
......@@ -14,14 +14,14 @@
-- File : topup_gating.vhdl
-- Revision : x.x.x
-- Created : December 05, 2012
-- Updated : October 29, 2013
-- Updated : February 03, 2014
-------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
-------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2013 Synchrotron Soleil
-- Copyright (C) 2012 - 2014 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
......@@ -150,7 +150,7 @@ architecture rtl_topup_gating of topup_gating is
process (p_reset, p_clk60MHz)
begin
if (p_reset = '1') then
s_cntHoldOffMax <= unsigned (c_topUpGateHoldOff_init);
s_cntHoldOffMax <= unsigned (c_wRegister_init(4));
s_rstCNT0 <= '0';
elsif (rising_edge(p_clk60MHz)) then
if (p_csw(0) = '1') then
......@@ -167,7 +167,7 @@ architecture rtl_topup_gating of topup_gating is
process (p_reset, p_clk60MHz)
begin
if (p_reset = '1') then
s_cntGateWidthMax <= unsigned (c_topUpGateWidth_init);
s_cntGateWidthMax <= unsigned (c_wRegister_init(5));
s_rstCNT1 <= '0';
elsif (rising_edge(p_clk60MHz)) then
if (p_csw(1) = '1') then
......
fpga/sources/top.vhdl
View file @ 4563b9be
This diff is collapsed.
fpga/sources/type_lib.vhdl
View file @ 4563b9be
......@@ -7,14 +7,14 @@
-- File : type_lib.vhdl
-- Revision : x.x.x
-- Created : Decemeber 04, 2013
-- Updated : December 06, 2013
-- Updated : February 03, 2014
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2013 Synchrotron Soleil
-- Copyright (C) 2012 - 2014 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
......@@ -44,7 +44,7 @@ use ieee.numeric_std.all;
--------------------------------------------------------------------------------
package type_lib is
type register_array is array (0 to 13) of std_logic_vector (31 downto 0);
type register_array is array (0 to 15) of std_logic_vector (31 downto 0);
type add_register_array is array (0 to 13) of std_logic_vector (9 downto 2);
end package type_lib;
......
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