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Commit 69f29835 authored by Jean-Paul Ricaud's avatar Jean-Paul Ricaud
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VHDL : added LINAC multi-pulse function 

SCH : corrected typo error

 On branch development

	modified:   fpga/sources/outputmux.vhdl
	modified:   fpga/sources/registers_init.vhdl
	modified:   fpga/sources/src_duplication/dup_config.txt
	modified:   fpga/sources/src_duplication/dup_leds.vhdl
	modified:   fpga/sources/src_duplication/dup_monitoring.vhdl
	modified:   fpga/sources/src_duplication/dup_top.vhdl
	new file:   fpga/sources/src_linacMP/linacMP_andpulses.vhdl
	new file:   fpga/sources/src_linacMP/linacMP_config.txt
	new file:   fpga/sources/src_linacMP/linacMP_leds.vhdl
	new file:   fpga/sources/src_linacMP/linacMP_monitoring.vhdl
	new file:   fpga/sources/src_linacMP/linacMP_top.vhdl
	modified:   fpga/sources/src_test/test_config.txt
	modified:   fpga/sources/src_topup/topup_config.txt
	modified:   fpga/sources/top.vhdl
	modified:   sch/Expansion_connectors.sch
	modified:   sch/FPGA.sch
	modified:   sch/FPGA_config.sch
	modified:   sch/Osc.sch
	modified:   sch/PCI9030.sch
	modified:   sch/cPCI_connector.sch
	modified:   sch/input.sch
	modified:   sch/outputs.sch
	modified:   sch/psu.sch
	modified:   sch/reset.sch
	modified:   sch/timex3_sch-cache.lib
	modified:   sch/timex3_sch.pro
	modified:   sch/timex3_sch.sch
	modified:   sch/top.sch
parent 5fc0ff0a
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fpga/sources/outputmux.vhdl
View file @ 69f29835
......@@ -4,13 +4,15 @@
--------------------------------------------------------------------------------
-- Description : Output multiplexer
-- SW 5-4-3-2-1-0
-- 1-1-1-1-1-1 : board test
-- 0-0-0-0-1-0 : LINAC multipulse
-- 0-0-0-0-0-1 : top-up trigger
-- 0-0-0-0-0-0 : duplication
--------------------------------------------------------------------------------
-- File : outputmux.vhdl
-- Revision : x.x.x
-- Created : October 26, 2012
-- Updated : Febuary 22, 2013
-- Updated : March 14, 2013
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -48,22 +50,26 @@ use ieee.numeric_std.all;
entity outputMux is
port (
-- Duplication block
p_dup_outTTL : in std_logic_vector (4 downto 0);
p_dup_outPECL : in std_logic_vector (4 downto 0);
p_dup_LED : in std_logic_vector (1 downto 0);
p_dup_outTTL : in std_logic_vector (4 downto 0);
p_dup_outPECL : in std_logic_vector (4 downto 0);
p_dup_LED : in std_logic_vector (1 downto 0);
-- Top-up block
p_topup_outTTL : in std_logic_vector (4 downto 0);
p_topUp_outPECL : in std_logic_vector (4 downto 0);
p_topUp_LED : in std_logic_vector (1 downto 0);
p_topup_outTTL : in std_logic_vector (4 downto 0);
p_topUp_outPECL : in std_logic_vector (4 downto 0);
p_topUp_LED : in std_logic_vector (1 downto 0);
-- LINAC multipulse block
p_linacMP_outTTL : in std_logic_vector (4 downto 0);
p_linacMP_outPECL : in std_logic_vector (4 downto 0);
p_linacMP_LED : in std_logic_vector (1 downto 0);
-- Test block
p_test_outTTL : in std_logic_vector (4 downto 0);
p_test_outPECL : in std_logic_vector (4 downto 0);
p_test_LED : in std_logic_vector (1 downto 0);
p_test_outTTL : in std_logic_vector (4 downto 0);
p_test_outPECL : in std_logic_vector (4 downto 0);
p_test_LED : in std_logic_vector (1 downto 0);
-- Mux block
p_mux_SWsel : in std_logic_vector (5 downto 0);
p_mux_outTTL : out std_logic_vector (4 downto 0);
p_mux_outPECL : out std_logic_vector (4 downto 0);
p_mux_outLED : out std_logic_vector (1 downto 0)
p_mux_SWsel : in std_logic_vector (5 downto 0);
p_mux_outTTL : out std_logic_vector (4 downto 0);
p_mux_outPECL : out std_logic_vector (4 downto 0);
p_mux_outLED : out std_logic_vector (1 downto 0)
);
end entity outputMux;
......@@ -91,23 +97,26 @@ architecture rtl_outputMux of outputMux is
-- TTL ouuputs selection
with p_mux_SWsel select
p_mux_outTTL <=
p_dup_outTTL when "000000",
p_topUp_outTTL when "000001",
p_test_outTTL when OTHERS;
p_dup_outTTL when "000000",
p_topUp_outTTL when "000001",
p_linacMP_outTTL when "000010",
p_test_outTTL when OTHERS;
-- LVPECL ouuputs selection
with p_mux_SWsel select
p_mux_outPECL <=
p_dup_outPECL when "000000",
p_topUp_outPECL when "000001",
p_test_outPECL when OTHERS;
p_dup_outPECL when "000000",
p_topUp_outPECL when "000001",
p_linacMP_outPECL when "000010",
p_test_outPECL when OTHERS;
-- LEDs outputs selection
with p_mux_SWsel select
p_mux_outLED <=
p_dup_LED when "000000",
p_topUp_LED when "000001",
p_test_LED when OTHERS;
p_dup_LED when "000000",
p_topUp_LED when "000001",
p_linacMP_LED when "000010",
p_test_LED when OTHERS;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
......
fpga/sources/registers_init.vhdl
View file @ 69f29835
......@@ -9,7 +9,7 @@
-- File : registers_init.vhdl
-- Revision : x.x.x
-- Created : March 06, 2013
-- Updated : March 11, 2013
-- Updated : March 14, 2013
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -55,12 +55,12 @@ package registers_init is
constant c_cmd_reg_init : std_logic_vector (31 downto 0) := X"00000000";
constant c_wRegister0_init : std_logic_vector (31 downto 0) := X"00000000";
constant c_wRegister1_init, c_dupMissingPulseDelay_init : std_logic_vector (31 downto 0) := X"000493E0";
constant c_wRegister2_init, c_topUpMaxPostTopUpDelay_init : std_logic_vector (31 downto 0) := X"000668A0";
constant c_wRegister2_init, c_topUpMaxPostTopUpDelay_init : std_logic_vector (31 downto 0) := X"000493E0";
constant c_wRegister3_init, c_topUpMaxPreTopUpDelay_init : std_logic_vector (31 downto 0) := X"0001D4C0";
constant c_wRegister4_init, c_topUpGateHoldOff_init : std_logic_vector (31 downto 0) := X"000007D0";
constant c_wRegister5_init, c_topUpGateWidth_init : std_logic_vector (31 downto 0) := X"000001F4";
constant c_wRegister6_init : std_logic_vector (31 downto 0) := X"00000000";
constant c_wRegister7_init : std_logic_vector (31 downto 0) := X"00000000";
constant c_wRegister7_init, c_linacMPMissingPulseDelay_init : std_logic_vector (31 downto 0) := X"000493E0";
constant c_wRegister8_init : std_logic_vector (31 downto 0) := X"00000000";
constant c_wRegister9_init : std_logic_vector (31 downto 0) := X"00000000";
constant c_wRegister10_init : std_logic_vector (31 downto 0) := X"00000000";
......
fpga/sources/src_duplication/dup_config.txt
View file @ 69f29835
------------------------------------------------------------------------------
-- Title : Configuration of TimEx v2
-- Title : Configuration of TimEX3
-- Project : TimEX3
-------------------------------------------------------------------------------
-- Description : differents configuration of the TimEx v2
-- Description : Differents configuration of the TimEX3
-------------------------------------------------------------------------------
-- File : dup_config.txt
-- Revision : x.x.x
......@@ -36,7 +36,7 @@
--------------------------------------------------------------------------------
===============================================================================
Configuration : duplication 1 input - 4 output
Configuration : duplication 1 input to 4 outputs
SW : 5-4-3-2-1-0
0-0-0-0-0-0
......@@ -48,7 +48,7 @@ IO3 : output - duplicated signal
IO4 : output - duplicated signal
Green LED on = OK
Red LED on = missing trigger on the input
Red LED on = missing trigger on the input
R3, R28, R29, R30, R31 => Qty = 1
R6, R16, R17, R18, R19 => Qty = 0
......
fpga/sources/src_duplication/dup_leds.vhdl
View file @ 69f29835
--------------------------------------------------------------------------------
-- Title : p_leds - duplication
-- Title : Leds
-- Project : TimEX3
--------------------------------------------------------------------------------
-- Description : p_leds management
-- Description : Leds management
--
-- | OFF | ON | BLINKING
-- ======|=====================|=====================|=====================
......
fpga/sources/src_duplication/dup_monitoring.vhdl
View file @ 69f29835
......@@ -2,7 +2,7 @@
-- Title : Monitoring of input signal
-- Project : TimEX3
--------------------------------------------------------------------------------
-- Description : The input signal is monotored at a frequency of 1Hz.
-- Description : The input signal is monotored at a frequency of 1kHz.
-- A 32 bits conter is used to save the time between two synchroization
-- pulses.
--------------------------------------------------------------------------------
......
fpga/sources/src_duplication/dup_top.vhdl
View file @ 69f29835
......@@ -90,7 +90,7 @@ architecture rtl_dup_top of dup_top is
);
-- Signal monitoring block
-- The time betwwen 2 input pulses in stored in MONITOR register (in seconds)
-- The time betwwen 2 input pulses in stored in MONITOR register (in ms)
pulseMonitor : entity work.dup_monitoring (rtl_dup_monitoring)
port map (
p_inTTL => p_dup_inTTL, -- TTL input
......
fpga/sources/src_linacMP/linacMP_andpulses.vhdl 0 → 100755
View file @ 69f29835
--------------------------------------------------------------------------------
-- Title : And between inputs pulses
-- Project : TimEX3
--------------------------------------------------------------------------------
-- Description : And between inputs pulses
--------------------------------------------------------------------------------
-- File : linacMP_andpulses.vhd
-- Revision : x.x.x
-- Created : March 14, 2013
-- Updated : March 14, 2013
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2013 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Modifications :
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
--------------------------------- ENTITY ---------------------------------------
--------------------------------------------------------------------------------
entity linacMP_andPulses is
port (
p_inTTL : in std_logic_vector (3 downto 0); -- TTL inputs
p_outTTL : out std_logic -- TTL output
);
end linacMP_andPulses;
--------------------------------------------------------------------------------
------------------------------- ARCHITECTURE -----------------------------------
-- TTL duplication
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture rtl_linacMP_andPulses of linacMP_andPulses is
-- constant
-- signal
------------------------------------------------------------------------------
--------------------------------- Main ---------------------------------------
------------------------------------------------------------------------------
begin
p_outTTL <= p_inTTL(3) and p_inTTL(2) and p_inTTL(1) and p_inTTL(0);
end rtl_linacMP_andPulses;
fpga/sources/src_linacMP/linacMP_config.txt 0 → 100755
View file @ 69f29835
------------------------------------------------------------------------------
-- Title : Configuration of TimEX3
-- Project : TimEX3
-------------------------------------------------------------------------------
-- Description : Differents configuration of the TimEX3
-------------------------------------------------------------------------------
-- File : linacMP_config.txt
-- Revision : x.x.x
-- Created : March 14, 2013
-- Updated : March 14, 2013
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2013 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Modifications :
--
--------------------------------------------------------------------------------
===============================================================================
Configuration : LINAC multi pulses 4 inputs - 1 output
SW : 5-4-3-2-1-0
0-0-0-0-1-0
IO0 : input - input signal
IO1 : input - delayed signal
IO2 : input - delayed signal
IO3 : input - delayed signal
IO4 : output - anded pulses
Green LED on = OK
Red LED on = missing trigger on the input
R3, R16, R17, R18, R31 => Qty = 1
R6, R28, R29, R3, R19 => Qty = 0
===============================================================================
fpga/sources/src_linacMP/linacMP_leds.vhdl 0 → 100755
View file @ 69f29835
--------------------------------------------------------------------------------
-- Title : Leds
-- Project : TimEX3
--------------------------------------------------------------------------------
-- Description : leds management
--
-- | OFF | ON | BLINKING
-- ======|=====================|=====================|=====================
-- GREEN | FPGA not configured | OK | synchro pulse
-- | | | detected
-- ======|=====================|=====================|=====================
-- RED | OK | no synchro pulse |
-- | | for more than n ms |
-- ======|=====================|=====================|=====================
--
--------------------------------------------------------------------------------
-- File : linacMP_leds.vhdl
-- Revision : x.x.x
-- Created : March 14, 2013
-- Updated : March 14, 2013
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2013 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Modifications :
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.registers_init.all;
--------------------------------------------------------------------------------
--------------------------------- ENTITY ---------------------------------------
--------------------------------------------------------------------------------
entity linacMP_leds is
port (
p_inTTL : in std_logic; -- input TTL
p_clk1kHz : in std_logic;
p_clk500mHz : in std_logic;
p_clk60MHz : in std_logic;
p_missingPulseDelay : in std_logic_vector (31 downto 0);
p_csw : in std_logic;
p_reset : in std_logic;
p_led : out std_logic_vector (1 downto 0)
);
end entity linacMP_leds;
--------------------------------------------------------------------------------
------------------------------- ARCHITECTURE -----------------------------------
--------------------------------------------------------------------------------
architecture rtl_linacMP_leds of linacMP_leds is
------------------------------------------------------------------------------
-- constant
------------------------------------------------------------------------------
constant s_cnt1max : unsigned (3 downto 0) := "1011"; -- 5s
------------------------------------------------------------------------------
-- signal
------------------------------------------------------------------------------
signal s_cnt1 : unsigned (3 downto 0); -- counter
signal s_cnt2 : unsigned (31 downto 0); -- counter
signal s_cnt2max : unsigned (31 downto 0); -- max delay
signal s_greenLedON : std_logic;
signal s_blink : std_logic;
signal s_rstCNT : std_logic; -- reset the conter after a software delay update
------------------------------------------------------------------------------
--------------------------------- Main ---------------------------------------
------------------------------------------------------------------------------
begin
-- Green LED
-- The green LED is blinked for 5s after a reset or after a input pulse is
-- dtected. It remains ON in other cases.
process (p_reset, p_inTTL, p_clk500mHz)
begin
if ((p_inTTL = '1') or (p_reset = '1')) then
s_cnt1 <= (OTHERS => '0');
s_greenLedON <= '1'; -- green LED ON
s_blink <= '1'; -- blink the green LED
elsif (rising_edge(p_clk500mHz)) then
if (s_blink = '1') then
if (s_cnt1 < s_cnt1max) then
s_cnt1 <= s_cnt1 + 1;
s_greenLedON <= not s_greenLedON; -- blink the green LED
s_blink <= '1'; -- keep blinking
else
s_cnt1 <= s_cnt1; -- keep the max value
s_greenLedON <= '1'; -- green LED ON
s_blink <= '0'; -- stop blinking
end if;
else
s_cnt1 <= s_cnt1; -- keep the max value
s_greenLedON <= '1'; -- green LED ON
s_blink <= '0'; -- stop blinking
end if;
end if;
end process;
-- Red LED
-- The red LED is off after a reset. It gos ON if no input signal is detected
-- after n mn.
process (p_reset, p_inTTL, s_rstCNT, p_clk1kHz)
begin
if ((p_inTTL = '1') or (p_reset = '1') or (s_rstCNT = '1')) then
s_cnt2 <= (OTHERS => '0');
p_led(0) <= '0'; -- red LED OFF
elsif (rising_edge(p_clk1kHz)) then
if (s_cnt2 < s_cnt2max) then
s_cnt2 <= s_cnt2 + 1;
p_led(0) <= '0'; -- red LED OFF
else
s_cnt2 <= s_cnt2; -- keep the max value in case of overflow
p_led(0) <= '1'; -- red LED ON
end if;
end if;
end process;
-- Latch from the register the maximum delay before a missing synchro pulse
-- is signaled
process (p_reset, p_clk60MHz)
begin
if (p_reset = '1') then
s_cnt2max <= unsigned (c_dupMissingPulseDelay_init);
s_rstCNT <= '0';
elsif (rising_edge(p_clk60MHz)) then
if (p_csw = '1') then
s_cnt2max <= unsigned (p_missingPulseDelay);
s_rstCNT <= '1';
else
s_cnt2max <= s_cnt2max;
s_rstCNT <= '0';
end if;
end if;
end process;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
p_led(1) <= s_greenLedON;
end architecture rtl_linacMP_leds;
fpga/sources/src_linacMP/linacMP_monitoring.vhdl 0 → 100755
View file @ 69f29835
--------------------------------------------------------------------------------
-- Title : Monitoring of input(0) signal
-- Project : TimEX3
--------------------------------------------------------------------------------
-- Description : The input signal is monotored at a frequency of 1kHz.
-- A 32 bits conter is used to save the time between two synchroization
-- pulses.
--------------------------------------------------------------------------------
-- File : linacMP_monitoring.vhdl
-- Revision : x.x.x
-- Created : March 14, 2013
-- Updated : March 14, 2013
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2013 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Modifications :
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
--------------------------------- ENTITY ---------------------------------------
--------------------------------------------------------------------------------
entity linacMP_monitoring is
port (
p_inTTL : in std_logic; -- TTL input
p_clk1kHz : in std_logic;
p_reset : in std_logic;
p_monitor : out std_logic_vector (31 downto 0) -- register with the time
-- value between two pulses
);
end linacMP_monitoring;
--------------------------------------------------------------------------------
------------------------------- ARCHITECTURE -----------------------------------
--------------------------------------------------------------------------------
architecture rtl_linacMP_monitoring of linacMP_monitoring is
------------------------------------------------------------------------------
-- constant
------------------------------------------------------------------------------
constant s_cntmax : unsigned (31 downto 0) := X"FFFFFFFF";
------------------------------------------------------------------------------
-- signal
------------------------------------------------------------------------------
signal s_cnt : unsigned (31 downto 0); -- counter
------------------------------------------------------------------------------
--------------------------------- Main ---------------------------------------
------------------------------------------------------------------------------
begin
process (p_reset, p_inTTL, p_clk1kHz)
begin
if ((p_inTTL = '1') or (p_reset = '1')) then
s_cnt <= (OTHERS => '0');
elsif (falling_edge(p_clk1kHz)) then
if (s_cnt < s_cntmax) then
s_cnt <= s_cnt + 1;
else
s_cnt <= s_cnt; -- keep the max value in case of overflow
end if;
end if;
end process;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
p_monitor <= std_logic_vector(s_cnt);
end rtl_linacMP_monitoring;
fpga/sources/src_linacMP/linacMP_top.vhdl 0 → 100755
View file @ 69f29835
--------------------------------------------------------------------------------
-- Title : Top - LINAC multipulse function
-- Project : TimEX3
--------------------------------------------------------------------------------
-- Description : Top sheet of the LINAC multipluse block
-- inTTL(3 donwto 0) are anded to produce a multipulse on outTTL(4)
-- outTTL(3 donwto 0) are not used as the board IO connectors are hard
-- configured as inputs
--------------------------------------------------------------------------------
-- File : linacMP_top.vhdl
-- Revision : x.x.x
-- Created : March 14, 2013
-- Updated : March 14, 2013
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2013 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the Lesser GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Modifications :
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
--------------------------------- ENTITY ---------------------------------------
--------------------------------------------------------------------------------
entity linacMP_top is
port (
p_linacMP_inTTL : in std_logic_vector (3 downto 0); -- TTL inputs
p_linacMP_outTTL : out std_logic_vector (4 downto 0); -- TTL outputs
p_linacMP_outPECL : out std_logic_vector (4 downto 0); -- LVPECL outputs
p_linacMP_clk1kHz : in std_logic;
p_linacMP_clk500mHz : in std_logic;
p_linacMP_clk60MHz : in std_logic;
p_linacMP_missingPulseDelay : in std_logic_vector (31 downto 0);
p_linacMP_csw : in std_logic;
p_linacMP_reset : in std_logic;
p_linacMP_pulseMon : out std_logic_vector (31 downto 0); -- pulses monitor
p_linacMP_led : out std_logic_vector (1 downto 0)
);
end entity linacMP_top;
--------------------------------------------------------------------------------
------------------------------- ARCHITECTURE -----------------------------------
--------------------------------------------------------------------------------
architecture rtl_linacMP_top of linacMP_top is
------------------------------------------------------------------------------
-- constant
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- signal
------------------------------------------------------------------------------
signal s_impulse : std_logic; -- detection of impulse
------------------------------------------------------------------------------
--------------------------------- Main ---------------------------------------
------------------------------------------------------------------------------
begin
-- And between the four inputs
andPulses : entity work.linacMP_andPulses (rtl_linacMP_andPulses)
port map (
p_inTTL => p_linacMP_inTTL, -- TTL in
p_outTTL => p_linacMP_outTTL(4) -- TTL out
);
-- Signal monitoring block
-- The time betwwen 2 input(0) pulses in stored in MONITOR register (in ms)
pulseMonitor : entity work.linacMP_monitoring (rtl_linacMP_monitoring)
port map (
p_inTTL => p_linacMP_inTTL(0), -- TTL input
p_clk1kHz => p_linacMP_clk1kHz,
p_reset => p_linacMP_reset,
p_monitor => p_linacMP_pulseMon -- register with the time value between two pulses
);
-- LEDs management for the duplication block
-- The green LED is blinked for 5s after a reset or after a input pulse is
-- dtected. It remains ON in other cases.
-- The red LED is off after a reset. It gos ON if no input signal is detected
-- after delay defined in the missingPulseDelay register.
leds : entity work.linacMP_leds (rtl_linacMP_leds)
port map (
p_inTTL => p_linacMP_inTTL(0), -- TTL input
p_clk1kHz => p_linacMP_clk1kHz,
p_clk500mHz => p_linacMP_clk500mHz,
p_clk60MHz => p_linacMP_clk60MHz,
p_missingPulseDelay => p_linacMP_missingPulseDelay,
p_csw => p_linacMP_csw,
p_reset => p_linacMP_reset,
p_led => p_linacMP_led
);
------------------------------------------------------------------------------
------------------------------------------------------------------------------
p_linacMP_outPECL (4 downto 0) <= "00000";
p_linacMP_outTTL (3 downto 0) <= "0000";
end architecture rtl_linacMP_top;
fpga/sources/src_test/test_config.txt
View file @ 69f29835
------------------------------------------------------------------------------
-- Title : Configuration of TimEx v2
-- Title : Configuration of TimEX3
-- Project : TimEX3
-------------------------------------------------------------------------------
-- Description : differents configuration of the TimEx v2
-- Description : differents configuration of the TimEX3
-------------------------------------------------------------------------------
-- File : dup_config.txt
-- File : test_config.txt
-- Revision : x.x.x
-- Created : November 20, 2012
-- Updated : November 20, 2012
-- Created : Febuary 22, 2013
-- Updated : Febuary 22, 2013
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2012 - Synchrotron Soleil
-- Copyright (C) 2012 - 2013 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
......@@ -48,7 +48,7 @@ IO3 : output - duplicated signal
IO4 : output - duplicated signal
Green LED on = OK
Red LED on = missing trigger on the input
Red LED on = missing trigger on the input
R3, R28, R29, R30, R31 => Qty = 1
R6, R16, R17, R18, R19 => Qty = 0
......
fpga/sources/src_topup/topup_config.txt
View file @ 69f29835
------------------------------------------------------------------------------
-- Title : Configuration of TimEx v2
-- Project : TimEX version 2
-- Title : Configuration of TimEX3
-- Project : TimEX3
-------------------------------------------------------------------------------
-- Description : differents configuration of the TimEx v2
-- Description : Differents configuration of the TimEX3
-------------------------------------------------------------------------------
-- File : topup_config.txt
-- Revision : x.x.x
......@@ -45,7 +45,7 @@ IO0 : input - pre top-up
IO1 : input - post top-up
IO2 : output - negative gating
IO3 : output - positive gating
IO4 : output - error output
IO4 : output - machine gating
Green LED on = waiting for injection
Green LEd blinking = injection going on
......
fpga/sources/top.vhdl
View file @ 69f29835
This diff is collapsed.
sch/Expansion_connectors.sch
View file @ 69f29835
EESchema Schematic File Version 2 date 14/03/2013 14:51:25
EESchema Schematic File Version 2 date 15/03/2013 15:39:09
LIBS:capacitors_aluminium
LIBS:capacitors_ceramic
LIBS:capacitors_tantalum
......@@ -35,7 +35,7 @@ $Descr A3 16535 11700
encoding utf-8
Sheet 6 12
Title "TimEX3"
Date "14 mar 2013"
Date "15 mar 2013"
Rev "1.0"
Comp "Expansion connectors"
Comment1 ""
......@@ -1736,7 +1736,7 @@ C8 95 09 26 98 E0 FF 17 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13
4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04
13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C
44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A FC 5F B8 67 24
AA B9 CE D2 63 00 00 00 00 49 45 4E 44 AE 42 60 82 28 $EndBitmap
AA B9 CE D2 63 00 00 00 00 49 45 4E 44 AE 42 60 82 F8 $EndBitmap
EndData
$EndBitmap
Text Notes 14850 10150 0 60 ~ 0
......
sch/FPGA.sch
View file @ 69f29835
EESchema Schematic File Version 2 date 14/03/2013 14:51:25
EESchema Schematic File Version 2 date 15/03/2013 15:39:09
LIBS:capacitors_aluminium
LIBS:capacitors_ceramic
LIBS:capacitors_tantalum
......@@ -35,7 +35,7 @@ $Descr A3 16535 11700
encoding utf-8
Sheet 5 12
Title "TimEX3"
Date "14 mar 2013"
Date "15 mar 2013"
Rev "1.0"
Comp "FPGA IOs"
Comment1 ""
......@@ -2909,7 +2909,7 @@ C8 95 09 26 98 E0 FF 17 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13
4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04
13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C
44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A FC 5F B8 67 24
AA B9 CE D2 63 00 00 00 00 49 45 4E 44 AE 42 60 82 28 $EndBitmap
AA B9 CE D2 63 00 00 00 00 49 45 4E 44 AE 42 60 82 F8 $EndBitmap
EndData
$EndBitmap
$EndSCHEMATC
sch/FPGA_config.sch
View file @ 69f29835
EESchema Schematic File Version 2 date 14/03/2013 14:51:25
EESchema Schematic File Version 2 date 15/03/2013 15:39:09
LIBS:capacitors_aluminium
LIBS:capacitors_ceramic
LIBS:capacitors_tantalum
......@@ -35,7 +35,7 @@ $Descr A3 16535 11700
encoding utf-8
Sheet 7 12
Title "TimEX3"
Date "14 mar 2013"
Date "15 mar 2013"
Rev "1.0"
Comp "FPGA config and power supply"
Comment1 ""
......@@ -3674,7 +3674,7 @@ C8 95 09 26 98 E0 FF 17 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13
4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04
13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C
44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A FC 5F B8 67 24
AA B9 CE D2 63 00 00 00 00 49 45 4E 44 AE 42 60 82 28 $EndBitmap
AA B9 CE D2 63 00 00 00 00 49 45 4E 44 AE 42 60 82 0F $EndBitmap
EndData
$EndBitmap
$EndSCHEMATC
sch/Osc.sch
View file @ 69f29835
EESchema Schematic File Version 2 date 14/03/2013 14:51:25
EESchema Schematic File Version 2 date 15/03/2013 15:39:09
LIBS:capacitors_aluminium
LIBS:capacitors_ceramic
LIBS:capacitors_tantalum
......@@ -35,7 +35,7 @@ $Descr A3 16535 11700
encoding utf-8
Sheet 10 12
Title "TimEX3"
Date "14 mar 2013"
Date "15 mar 2013"
Rev "1.0"
Comp "Oscillators"
Comment1 ""
......@@ -2092,7 +2092,7 @@ C8 95 09 26 98 E0 FF 17 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13
4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04
13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C
44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A FC 5F B8 67 24
AA B9 CE D2 63 00 00 00 00 49 45 4E 44 AE 42 60 82 28 $EndBitmap
AA B9 CE D2 63 00 00 00 00 49 45 4E 44 AE 42 60 82 04 $EndBitmap
EndData
$EndBitmap
$EndSCHEMATC
sch/PCI9030.sch
View file @ 69f29835
EESchema Schematic File Version 2 date 14/03/2013 14:51:25
EESchema Schematic File Version 2 date 15/03/2013 15:39:09
LIBS:capacitors_aluminium
LIBS:capacitors_ceramic
LIBS:capacitors_tantalum
......@@ -35,7 +35,7 @@ $Descr A3 16535 11700
encoding utf-8
Sheet 8 12
Title "TimEX3"
Date "14 mar 2013"
Date "15 mar 2013"
Rev "1.0"
Comp "PLX PCI9030 cPCI interface"
Comment1 ""
......@@ -4907,7 +4907,7 @@ C8 95 09 26 98 E0 FF 17 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13
4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04
13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C
44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A FC 5F B8 67 24
AA B9 CE D2 63 00 00 00 00 49 45 4E 44 AE 42 60 82 28 $EndBitmap
AA B9 CE D2 63 00 00 00 00 49 45 4E 44 AE 42 60 82 0C $EndBitmap
EndData
$EndBitmap
Text Notes 14850 10150 0 60 ~ 0
......
sch/cPCI_connector.sch
View file @ 69f29835
EESchema Schematic File Version 2 date 14/03/2013 14:51:25
EESchema Schematic File Version 2 date 15/03/2013 15:39:09
LIBS:capacitors_aluminium
LIBS:capacitors_ceramic
LIBS:capacitors_tantalum
......@@ -35,7 +35,7 @@ $Descr A3 16535 11700
encoding utf-8
Sheet 9 12
Title "TimEX3"
Date "14 mar 2013"
Date "15 mar 2013"
Rev "1.0"
Comp "cPCI connector"
Comment1 ""
......@@ -3151,7 +3151,7 @@ C8 95 09 26 98 E0 FF 17 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13
4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04
13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C
44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A FC 5F B8 67 24
AA B9 CE D2 63 00 00 00 00 49 45 4E 44 AE 42 60 82 28 $EndBitmap
AA B9 CE D2 63 00 00 00 00 49 45 4E 44 AE 42 60 82 0A $EndBitmap
EndData
$EndBitmap
Text Notes 14850 10150 0 60 ~ 0
......
sch/input.sch
View file @ 69f29835
EESchema Schematic File Version 2 date 14/03/2013 14:51:25
EESchema Schematic File Version 2 date 15/03/2013 15:39:09
LIBS:capacitors_aluminium
LIBS:capacitors_ceramic
LIBS:capacitors_tantalum
......@@ -35,7 +35,7 @@ $Descr A3 16535 11700
encoding utf-8
Sheet 3 12
Title "TimEX3"
Date "14 mar 2013"
Date "15 mar 2013"
Rev "1.0"
Comp "Default TTL input"
Comment1 ""
......@@ -2348,7 +2348,7 @@ C8 95 09 26 98 E0 FF 17 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13
4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04
13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C
44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A FC 5F B8 67 24
AA B9 CE D2 63 00 00 00 00 49 45 4E 44 AE 42 60 82 28 $EndBitmap
AA B9 CE D2 63 00 00 00 00 49 45 4E 44 AE 42 60 82 F8 $EndBitmap
EndData
$EndBitmap
Text Notes 14850 10150 0 60 ~ 0
......
sch/outputs.sch
View file @ 69f29835
EESchema Schematic File Version 2 date 14/03/2013 14:51:25
EESchema Schematic File Version 2 date 15/03/2013 15:39:09
LIBS:capacitors_aluminium
LIBS:capacitors_ceramic
LIBS:capacitors_tantalum
......@@ -35,7 +35,7 @@ $Descr A3 16535 11700
encoding utf-8
Sheet 4 12
Title "TimEX3"
Date "14 mar 2013"
Date "15 mar 2013"
Rev "1.0"
Comp "Outputs"
Comment1 ""
......@@ -50,7 +50,7 @@ Note : C13 capacitor\nreplaced by 0R
Text Notes 4750 4250 0 60 ~ 0
Note : C12 capacitor\nreplaced by 0R
Text Notes 4700 2000 0 60 ~ 0
Note : C2 capacitor\nreplaced by 0R
Note : C11 capacitor\nreplaced by 0R
Wire Wire Line
4400 9050 4400 9100
Connection ~ 4400 8450
......@@ -4144,7 +4144,7 @@ C8 95 09 26 98 E0 FF 17 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13
4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04
13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C
44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A FC 5F B8 67 24
AA B9 CE D2 63 00 00 00 00 49 45 4E 44 AE 42 60 82 28 $EndBitmap
AA B9 CE D2 63 00 00 00 00 49 45 4E 44 AE 42 60 82 F8 $EndBitmap
EndData
$EndBitmap
Text Notes 14850 10150 0 60 ~ 0
......
sch/psu.sch
View file @ 69f29835
EESchema Schematic File Version 2 date 14/03/2013 14:51:25
EESchema Schematic File Version 2 date 15/03/2013 15:39:09
LIBS:capacitors_aluminium
LIBS:capacitors_ceramic
LIBS:capacitors_tantalum
......@@ -35,7 +35,7 @@ $Descr A3 16535 11700
encoding utf-8
Sheet 12 12
Title "TimEX3"
Date "14 mar 2013"
Date "15 mar 2013"
Rev "1.0"
Comp "PSU"
Comment1 ""
......@@ -2689,7 +2689,7 @@ C8 95 09 26 98 E0 FF 17 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13
4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04
13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C
44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A FC 5F B8 67 24
AA B9 CE D2 63 00 00 00 00 49 45 4E 44 AE 42 60 82 28 $EndBitmap
AA B9 CE D2 63 00 00 00 00 49 45 4E 44 AE 42 60 82 10 $EndBitmap
EndData
$EndBitmap
$EndSCHEMATC
sch/reset.sch
View file @ 69f29835
EESchema Schematic File Version 2 date 14/03/2013 14:51:25
EESchema Schematic File Version 2 date 15/03/2013 15:39:09
LIBS:capacitors_aluminium
LIBS:capacitors_ceramic
LIBS:capacitors_tantalum
......@@ -35,7 +35,7 @@ $Descr A3 16535 11700
encoding utf-8
Sheet 11 12
Title "TimEX3"
Date "14 mar 2013"
Date "15 mar 2013"
Rev "1.0"
Comp "Reset & power monitor"
Comment1 ""
......@@ -2407,7 +2407,7 @@ C8 95 09 26 98 E0 FF 17 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13
4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04
13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C
44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A FC 5F B8 67 24
AA B9 CE D2 63 00 00 00 00 49 45 4E 44 AE 42 60 82 28 $EndBitmap
AA B9 CE D2 63 00 00 00 00 49 45 4E 44 AE 42 60 82 14 $EndBitmap
EndData
$EndBitmap
$EndSCHEMATC
sch/timex3_sch-cache.lib
View file @ 69f29835
EESchema-LIBRARY Version 2.3 Date: 14/03/2013 14:51:25
EESchema-LIBRARY Version 2.3 Date: 15/03/2013 15:39:09
#encoding utf-8
#
# 0R-0.125W-1P-0805
......
sch/timex3_sch.pro
View file @ 69f29835
update=05/02/2013 11:14:56
update=15/03/2013 15:43:03
last_client=eeschema
[pcbnew]
[pcbnew/libraries]
......
sch/timex3_sch.sch
View file @ 69f29835
EESchema Schematic File Version 2 date 14/03/2013 14:51:25
EESchema Schematic File Version 2 date 15/03/2013 15:39:08
LIBS:capacitors_aluminium
LIBS:capacitors_ceramic
LIBS:capacitors_tantalum
......@@ -35,7 +35,7 @@ $Descr A3 16535 11700
encoding utf-8
Sheet 1 12
Title "TimEX3"
Date "14 mar 2013"
Date "15 mar 2013"
Rev "1.0"
Comp "Cover sheet"
Comment1 ""
......@@ -4244,7 +4244,7 @@ C8 95 09 26 98 E0 FF 17 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13
4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04
13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C
44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A FC 5F B8 67 24
AA B9 CE D2 63 00 00 00 00 49 45 4E 44 AE 42 60 82 28 $EndBitmap
AA B9 CE D2 63 00 00 00 00 49 45 4E 44 AE 42 60 82 F8 $EndBitmap
EndData
$EndBitmap
$Sheet
......
sch/top.sch
View file @ 69f29835
EESchema Schematic File Version 2 date 14/03/2013 14:51:25
EESchema Schematic File Version 2 date 15/03/2013 15:39:09
LIBS:capacitors_aluminium
LIBS:capacitors_ceramic
LIBS:capacitors_tantalum
......@@ -35,7 +35,7 @@ $Descr A3 16535 11700
encoding utf-8
Sheet 2 12
Title "TimEX3"
Date "14 mar 2013"
Date "15 mar 2013"
Rev "1.0"
Comp "TOP"
Comment1 ""
......@@ -1918,7 +1918,7 @@ C8 95 09 26 98 E0 FF 17 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13
4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04
13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C
44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A 4C 44 C0 04 13 9C 6A FC 5F B8 67 24
AA B9 CE D2 63 00 00 00 00 49 45 4E 44 AE 42 60 82 28 $EndBitmap
AA B9 CE D2 63 00 00 00 00 49 45 4E 44 AE 42 60 82 F8 $EndBitmap
EndData
$EndBitmap
Text Notes 14800 10150 0 60 ~ 0
......
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