VHDL : corrected padding function

On branch development modified: fpga/sources/src_clkpadding/clkpadding_top.vhdl new file: fpga/sources/testbench/clkpadding_tb.vhdl modified: fpga/sources/top.vhdl

VHDL : corrected padding function
On branch development modified: fpga/sources/src_clkpadding/clkpadding_top.vhdl new file: fpga/sources/testbench/clkpadding_tb.vhdl modified: fpga/sources/top.vhdl
4810e869 · Jean-Paul Ricaud · 2d45d219 · 4810e869 · 4810e869 · 4810e869
Commit 4810e869 authored Oct 06, 2014 by Jean-Paul Ricaud
Showing with 502 additions and 16 deletions

clkpadding_top.vhdl fpga/sources/src_clkpadding/clkpadding_top.vhdl +26 -15

clkpadding_tb.vhdl fpga/sources/testbench/clkpadding_tb.vhdl +474 -0

top.vhdl fpga/sources/top.vhdl +2 -1

No files found.
--- a/fpga/sources/src_clkpadding/clkpadding_top.vhdl
+++ b/fpga/sources/src_clkpadding/clkpadding_top.vhdl
@@ -47,12 +47,13 @@ use ieee.numeric_std.all;
 --------------------------------------------------------------------------------
 entity clkPADDING_top is
  port (
-    p_clkPADDING_clk_mon : in  std_logic; -- monitored clock
-    p_clkPADDING_clk_sr  : in  std_logic; -- storage ring clock
-    p_clkPADDING_reset   : in  std_logic; -- global reset
-    p_clkPADDING_outTTL  : out std_logic_vector (4 downto 0); -- TTL outputs  -- output clock
-    p_clkPADDING_outPECL : out std_logic_vector (4 downto 0); -- LVPECL outputs
-    p_clkPADDING_LED     : out std_logic_vector (1 downto 0)
+    p_clkPADDING_clk500mHz : in  std_logic;
+    p_clkPADDING_clk_mon   : in  std_logic; -- monitored clock
+    p_clkPADDING_clk_sr    : in  std_logic; -- storage ring clock
+    p_clkPADDING_reset     : in  std_logic; -- global reset
+    p_clkPADDING_outTTL    : out std_logic_vector (4 downto 0); -- TTL outputs  -- output clock
+    p_clkPADDING_outPECL   : out std_logic_vector (4 downto 0); -- LVPECL outputs
+    p_clkPADDING_LED       : out std_logic_vector (1 downto 0)
  );
 end entity clkPADDING_top;

@@ -68,13 +69,15 @@ architecture rtl_clkPADDING_top of clkPADDING_top is
  ------------------------------------------------------------------------------
  -- signal
  ------------------------------------------------------------------------------
-  signal s_cnt1 : unsigned (10 downto 0); -- counter
-  signal s_cnt2 : unsigned (10 downto 0); -- counter
+  signal s_cnt1 : unsigned (8 downto 0); -- counter
+  signal s_cnt2 : unsigned (8 downto 0); -- counter

  signal s_start         : std_logic;
  signal s_underProgress : std_logic;
  signal s_clkPadding    : std_logic;
  signal s_reset         : std_logic;
+  signal s_led           : std_logic;
+  signal s_ledHold       : std_logic;

  ------------------------------------------------------------------------------
  --------------------------------- Main ---------------------------------------
@@ -88,7 +91,7 @@ architecture rtl_clkPADDING_top of clkPADDING_top is
      s_cnt1  <= (OTHERS => '0');
      s_start <= '0';
    elsif (rising_edge(p_clkPADDING_clk_sr)) then
-      if (s_cnt1 = X"1A7") then
+      if (s_cnt1 = X"1A9") then
        s_start <= '1';
        s_cnt1  <= s_cnt1;
      else
@@ -108,16 +111,12 @@ architecture rtl_clkPADDING_top of clkPADDING_top is
    elsif (rising_edge(p_clkPADDING_clk_sr)) then
      if ((s_start = '1') or (s_underProgress = '1')) then
        s_cnt2  <= s_cnt2 + 1;
-        if (s_cnt2 < X"2C1") then
+        if (s_cnt2 < X"1A2") then
          s_underProgress <= '1';
          s_clkPadding    <= '1';
-        elsif (s_cnt2 < X"32D") then
-          s_underProgress <= '1';
-          s_clkPadding    <= '0';
        else
          s_cnt2          <= (OTHERS => '0');
          s_underProgress <= '0';
-          s_clkPadding    <= '0';
        end if;
      else
        s_cnt2          <= (OTHERS => '0');
@@ -127,6 +126,18 @@ architecture rtl_clkPADDING_top of clkPADDING_top is
    end if;
  end process;

+  -- Trigger red LED
+  process (p_clkPADDING_reset, s_start, p_clkPADDING_clk500mHz)
+  begin
+    if ((p_clkPADDING_reset = '1') or (s_start = '1')) then
+      s_led     <= '1';
+      s_ledHold <= '1';
+    elsif (rising_edge(p_clkPADDING_clk500mHz)) then
+      s_led     <= s_ledHold;
+      s_ledHold <= '0';
+    end if;
+  end process;
+
  ------------------------------------------------------------------------------
  ------------------------------------------------------------------------------
  s_reset <= p_clkPADDING_reset or s_clkPadding;
@@ -139,7 +150,7 @@ architecture rtl_clkPADDING_top of clkPADDING_top is

  p_clkPADDING_outPECL(4 downto 0) <= "00000";

-  p_clkPADDING_led(0) <= s_underProgress;
+  p_clkPADDING_led(0) <= s_led; -- red LED
  p_clkPADDING_led(1) <= '1'; -- green LED ON

 end architecture rtl_clkPADDING_top;
--- a/fpga/sources/testbench/clkpadding_tb.vhdl
+++ b/fpga/sources/testbench/clkpadding_tb.vhdl
--- a/fpga/sources/top.vhdl
+++ b/fpga/sources/top.vhdl
@@ -7,7 +7,7 @@
 -- File     : top.vhd
 -- Revision : x.x.x
 -- Created  : October 26, 2012
-- Updated  : September 19, 2014
+-- Updated  : October 06, 2014
 --------------------------------------------------------------------------------
 -- Author       : Jean-Paul Ricaud
 -- Organization : Synchrotron Soleil
@@ -520,6 +520,7 @@ architecture rtl_top of top is
  -- Clock padding block
  clkPADDING : entity work.clkPADDING_top (rtl_clkPADDING_top)
    port map (
+      p_clkPADDING_clk500mHz       => s_clk500mhz,
      p_clkPADDING_clk_mon         => pin_inTTL(0),
      p_clkPADDING_clk_sr          => pin_inTTL(1),
      p_clkPADDING_reset           => s_reset,