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Commit 1e2013e4 authored by Jean-Paul Ricaud's avatar Jean-Paul Ricaud
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VHDL : multiplexed cPCI registers to overlap data depending on the configuration… 

VHDL : multiplexed cPCI registers to overlap data depending on the configuration (duplication, top-up, etc.)

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	modified:   fpga/TimEX3/TimEX3_eeprom.mcs
	modified:   fpga/sources/registers_init.vhdl
	modified:   fpga/sources/src_cPCI/cPCI_hermes.vhdl
	modified:   fpga/sources/src_cPCI/cPCI_registerMux.vhdl
	modified:   fpga/sources/src_cPCI/cPCI_statusManager.vhdl
	modified:   fpga/sources/top.vhdl
parent ffdb6900
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fpga/TimEX3/TimEX3_eeprom.mcs
View file @ 1e2013e4
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fpga/sources/registers_init.vhdl
View file @ 1e2013e4
......@@ -9,7 +9,7 @@
-- File : registers_init.vhdl
-- Revision : x.x.x
-- Created : March 06, 2013
-- Updated : November 14, 2013
-- Updated : November 26, 2013
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -51,7 +51,7 @@ package registers_init is
------------------------------------------------------------------------------
-- Write registers
constant c_test_reg_init : std_logic_vector (31 downto 0) := X"00000000";
constant c_status_reg_init : std_logic_vector (29 downto 0) := "000000000000000000000000000000";
constant c_status_reg_init : std_logic_vector (8 downto 0) := "000000000";
constant c_cmd_reg_init : std_logic_vector (31 downto 0) := X"00000000";
constant c_wRegister0_init : std_logic_vector (31 downto 0) := X"00000000";
constant c_wRegister1_init, c_dupMissingPulseDelay_init : std_logic_vector (31 downto 0) := X"000493E0";
......@@ -68,15 +68,7 @@ package registers_init is
constant c_wRegister12_init : std_logic_vector (31 downto 0) := X"00000000";
constant c_wRegister13_init : std_logic_vector (31 downto 0) := X"00000000";
constant c_cfgSW_mask0 : std_logic_vector (29 downto 0) := "000000000000000000000000000001"; -- duplication
constant c_cfgSW_mask1 : std_logic_vector (29 downto 0) := "000000000000000000000000011110"; -- top-up
constant c_cfgSW_mask2 : std_logic_vector (29 downto 0) := "000000000000000000000000100000"; -- LINAC multi-pulse
constant c_cfgSW_mask3 : std_logic_vector (29 downto 0) := "000000000000000000000111000000"; -- LINAC monitor
constant c_cfgSW_mask4 : std_logic_vector (29 downto 0) := "111111111111111111111111111111"; -- not used
constant c_cfgSW_mask5 : std_logic_vector (29 downto 0) := "111111111111111111111111111111"; -- not used
constant c_cfgSW_mask6 : std_logic_vector (29 downto 0) := "111111111111111111111111111111"; -- not used
constant c_cfgSW_mask7 : std_logic_vector (29 downto 0) := "111111111111111111111111111111"; -- not used
-- Read registers
constant c_board_id : std_logic_vector (31 downto 0) := X"4AC0FA5C"; -- board ID for TimEX3
constant c_firmware_rev : std_logic_vector (31 downto 0) := X"000000A0"; -- firmware's version
......
fpga/sources/src_cPCI/cPCI_hermes.vhdl
View file @ 1e2013e4
......@@ -22,7 +22,7 @@
-- File : cPCI_hermes.vhdl
-- Revision : x.x.x
-- Created : October 26, 2012
-- Updated : November 08, 2013
-- Updated : November 27, 2013
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -85,6 +85,7 @@ entity cPCI_hermes is
p_cmdReg : out std_logic_vector (31 downto 0); -- command register
p_config_reg : in std_logic_vector (31 downto 0); -- configurarion register
p_status_reg : in std_logic_vector (29 downto 0); -- bit 31 & 30 are reserved for access error
p_wRegister0 : out std_logic_vector (31 downto 0);
p_wRegister1 : out std_logic_vector (31 downto 0);
p_wRegister2 : out std_logic_vector (31 downto 0);
......@@ -99,6 +100,22 @@ entity cPCI_hermes is
p_wRegister11 : out std_logic_vector (31 downto 0);
p_wRegister12 : out std_logic_vector (31 downto 0);
p_wRegister13 : out std_logic_vector (31 downto 0);
p_wRegister0_init : in std_logic_vector (31 downto 0);
p_wRegister1_init : in std_logic_vector (31 downto 0);
p_wRegister2_init : in std_logic_vector (31 downto 0);
p_wRegister3_init : in std_logic_vector (31 downto 0);
p_wRegister4_init : in std_logic_vector (31 downto 0);
p_wRegister5_init : in std_logic_vector (31 downto 0);
p_wRegister6_init : in std_logic_vector (31 downto 0);
p_wRegister7_init : in std_logic_vector (31 downto 0);
p_wRegister8_init : in std_logic_vector (31 downto 0);
p_wRegister9_init : in std_logic_vector (31 downto 0);
p_wRegister10_init : in std_logic_vector (31 downto 0);
p_wRegister11_init : in std_logic_vector (31 downto 0);
p_wRegister12_init : in std_logic_vector (31 downto 0);
p_wRegister13_init : in std_logic_vector (31 downto 0);
p_rRegister0 : in std_logic_vector (31 downto 0);
p_rRegister1 : in std_logic_vector (31 downto 0);
p_rRegister2 : in std_logic_vector (31 downto 0);
......@@ -113,8 +130,8 @@ entity cPCI_hermes is
p_rRegister11 : in std_logic_vector (31 downto 0);
p_rRegister12 : in std_logic_vector (31 downto 0);
p_rRegister13 : in std_logic_vector (31 downto 0);
p_CSW : out std_logic_vector (14 downto 0); -- chip select of internal write transfert
p_CSR : out std_logic_vector (14 downto 0); -- chip select of internal read transfert
p_CSW : out std_logic_vector (15 downto 0); -- chip select of internal write transfert
p_CSR : out std_logic_vector (15 downto 0); -- chip select of internal read transfert
-- Other signals
p_reset : in std_logic -- reset in
);
......@@ -134,7 +151,7 @@ architecture rtl_cPCI_hermes of cPCI_hermes is
------------------------------------------------------------------------------
-- signal
------------------------------------------------------------------------------
signal s_csw : std_logic_vector (14 downto 0); -- chip select of internal write transfert
signal s_csw : std_logic_vector (15 downto 0); -- chip select of internal write transfert
signal s_startW : std_logic; -- write cycle start
signal s_setupW : std_logic; -- write cycle setup
signal s_strobeW : std_logic; -- write stobe
......@@ -194,20 +211,20 @@ architecture rtl_cPCI_hermes of cPCI_hermes is
if (p_reset = '1') then
s_test_reg <= c_test_reg_init;
s_cmd_reg <= c_cmd_reg_init;
s_wRegister0 <= c_wRegister0_init;
s_wRegister1 <= c_wRegister1_init;
s_wRegister2 <= c_wRegister2_init;
s_wRegister3 <= c_wRegister3_init;
s_wRegister4 <= c_wRegister4_init;
s_wRegister5 <= c_wRegister5_init;
s_wRegister6 <= c_wRegister6_init;
s_wRegister7 <= c_wRegister7_init;
s_wRegister8 <= c_wRegister8_init;
s_wRegister9 <= c_wRegister9_init;
s_wRegister10 <= c_wRegister10_init;
s_wRegister11 <= c_wRegister11_init;
s_wRegister12 <= c_wRegister12_init;
s_wRegister13 <= c_wRegister13_init;
s_wRegister0 <= p_wRegister0_init;
s_wRegister1 <= p_wRegister1_init;
s_wRegister2 <= p_wRegister2_init;
s_wRegister3 <= p_wRegister3_init;
s_wRegister4 <= p_wRegister4_init;
s_wRegister5 <= p_wRegister5_init;
s_wRegister6 <= p_wRegister6_init;
s_wRegister7 <= p_wRegister7_init;
s_wRegister8 <= p_wRegister8_init;
s_wRegister9 <= p_wRegister9_init;
s_wRegister10 <= p_wRegister10_init;
s_wRegister11 <= p_wRegister11_init;
s_wRegister12 <= p_wRegister12_init;
s_wRegister13 <= p_wRegister13_init;
s_csw <= (OTHERS => '0');
s_strobeW <= '0';
s_clearStatus <= '0';
......@@ -224,63 +241,63 @@ architecture rtl_cPCI_hermes of cPCI_hermes is
s_error(1) <= '0';
when c_add_cmd_reg =>
s_cmd_reg <= p_DATA;
s_csw <= "000000000000001";
s_csw <= "0000000000000001";
s_error(1) <= '0';
when c_add_register0 =>
s_wRegister0 <= p_DATA;
s_csw <= "000000000000010";
s_csw <= "0000000000000010";
s_error(1) <= '0';
when c_add_register1 =>
s_wRegister1 <= p_DATA;
s_csw <= "000000000000100";
s_csw <= "0000000000000100";
s_error(1) <= '0';
when c_add_register2 =>
s_wRegister2 <= p_DATA;
s_csw <= "000000000001000";
s_csw <= "0000000000001000";
s_error(1) <= '0';
when c_add_register3 =>
s_wRegister3 <= p_DATA;
s_csw <= "000000000010000";
s_csw <= "0000000000010000";
s_error(1) <= '0';
when c_add_register4 =>
s_wRegister4 <= p_DATA;
s_csw <= "000000000100000";
s_csw <= "0000000000100000";
s_error(1) <= '0';
when c_add_register5 =>
s_wRegister5 <= p_DATA;
s_csw <= "000000001000000";
s_csw <= "0000000001000000";
s_error(1) <= '0';
when c_add_register6 =>
s_wRegister6 <= p_DATA;
s_csw <= "000000010000000";
s_csw <= "0000000010000000";
s_error(1) <= '0';
when c_add_register7 =>
s_wRegister7 <= p_DATA;
s_csw <= "000000100000000";
s_csw <= "0000000100000000";
s_error(1) <= '0';
when c_add_register8 =>
s_wRegister8 <= p_DATA;
s_csw <= "000001000000000";
s_csw <= "0000001000000000";
s_error(1) <= '0';
when c_add_register9 =>
s_wRegister9 <= p_DATA;
s_csw <= "000010000000000";
s_csw <= "0000010000000000";
s_error(1) <= '0';
when c_add_register10 =>
s_wRegister10 <= p_DATA;
s_csw <= "000100000000000";
s_csw <= "0000100000000000";
s_error(1) <= '0';
when c_add_register11 =>
s_wRegister11 <= p_DATA;
s_csw <= "001000000000000";
s_csw <= "0001000000000000";
s_error(1) <= '0';
when c_add_register12 =>
s_wRegister12 <= p_DATA;
s_csw <= "010000000000000";
s_csw <= "0010000000000000";
s_error(1) <= '0';
when c_add_register13 =>
s_wRegister13 <= p_DATA;
s_csw <= "100000000000000";
s_csw <= "0100000000000000";
s_error(1) <= '0';
when others =>
s_error(1) <= '1';
......@@ -444,12 +461,12 @@ architecture rtl_cPCI_hermes of cPCI_hermes is
when c_add_firmware_reg =>
p_DATA <= c_firmware_rev;
s_error(0) <= '0';
when c_add_config_reg =>
p_DATA <= p_config_reg;
s_error(0) <= '0';
when c_add_test_reg =>
p_DATA <= s_test_reg;
s_error(0) <= '0';
when c_add_config_reg =>
p_DATA <= p_config_reg;
s_error(0) <= '0';
when c_add_status_reg =>
p_DATA <= s_status_reg;
s_error(0) <= '0';
......
fpga/sources/src_cPCI/cPCI_registerMux.vhdl
View file @ 1e2013e4
......@@ -13,7 +13,7 @@
-- File : cPCI_registerMux.vhdl
-- Revision : x.x.x
-- Created : November 17, 2013
-- Updated : November 18, 2013
-- Updated : November 27, 2013
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -45,6 +45,9 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.registers_init.all;
--------------------------------------------------------------------------------
--------------------------------- ENTITY ---------------------------------------
--------------------------------------------------------------------------------
......@@ -65,6 +68,22 @@ entity cPCI_registerMux is
p_wRegister11 : in std_logic_vector (31 downto 0);
p_wRegister12 : in std_logic_vector (31 downto 0);
p_wRegister13 : in std_logic_vector (31 downto 0);
p_wRegister0_init : out std_logic_vector (31 downto 0);
p_wRegister1_init : out std_logic_vector (31 downto 0);
p_wRegister2_init : out std_logic_vector (31 downto 0);
p_wRegister3_init : out std_logic_vector (31 downto 0);
p_wRegister4_init : out std_logic_vector (31 downto 0);
p_wRegister5_init : out std_logic_vector (31 downto 0);
p_wRegister6_init : out std_logic_vector (31 downto 0);
p_wRegister7_init : out std_logic_vector (31 downto 0);
p_wRegister8_init : out std_logic_vector (31 downto 0);
p_wRegister9_init : out std_logic_vector (31 downto 0);
p_wRegister10_init : out std_logic_vector (31 downto 0);
p_wRegister11_init : out std_logic_vector (31 downto 0);
p_wRegister12_init : out std_logic_vector (31 downto 0);
p_wRegister13_init : out std_logic_vector (31 downto 0);
p_rRegister0 : out std_logic_vector (31 downto 0);
p_rRegister1 : out std_logic_vector (31 downto 0);
p_rRegister2 : out std_logic_vector (31 downto 0);
......@@ -79,6 +98,7 @@ entity cPCI_registerMux is
p_rRegister11 : out std_logic_vector (31 downto 0);
p_rRegister12 : out std_logic_vector (31 downto 0);
p_rRegister13 : out std_logic_vector (31 downto 0);
-- Mux in / out
p_mux_wRegister0 : out std_logic_vector (31 downto 0);
p_mux_wRegister1 : out std_logic_vector (31 downto 0);
......@@ -94,6 +114,7 @@ entity cPCI_registerMux is
p_mux_wRegister11 : out std_logic_vector (31 downto 0);
p_mux_wRegister12 : out std_logic_vector (31 downto 0);
p_mux_wRegister13 : out std_logic_vector (31 downto 0);
p_mux_rRegister0 : in std_logic_vector (31 downto 0);
p_mux_rRegister1 : in std_logic_vector (31 downto 0);
p_mux_rRegister2 : in std_logic_vector (31 downto 0);
......@@ -108,7 +129,13 @@ entity cPCI_registerMux is
p_mux_rRegister11 : in std_logic_vector (31 downto 0);
p_mux_rRegister12 : in std_logic_vector (31 downto 0);
p_mux_rRegister13 : in std_logic_vector (31 downto 0);
-- Mux block
p_mux_csw : in std_logic_vector (15 downto 0); -- chip select of internal write transfert
p_mux_csr : in std_logic_vector (15 downto 0); -- chip select of internal read transfert
p_csw : out std_logic_vector (15 downto 0);
p_csr : out std_logic_vector (15 downto 0);
-- Congig pin
p_mux_SWsel : in std_logic_vector (5 downto 0)
);
end entity cPCI_registerMux;
......@@ -211,6 +238,57 @@ architecture rtl_cPCI_registerMux of cPCI_registerMux is
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Write registers init values mux
with p_mux_SWsel select
p_wRegister0_init <=
c_wRegister0_init when "000000",
c_wRegister2_init when "000001",
c_wRegister6_init when "000010",
c_wRegister8_init when "000011",
X"00000000" when OTHERS;
with p_mux_SWsel select
p_wRegister1_init <=
c_wRegister1_init when "000000",
c_wRegister3_init when "000001",
c_wRegister7_init when "000010",
c_wRegister9_init when "000011",
X"00000000" when OTHERS;
with p_mux_SWsel select
p_wRegister2_init <=
c_wRegister4_init when "000001",
c_wRegister10_init when "000011",
X"00000000" when OTHERS;
with p_mux_SWsel select
p_wRegister3_init <=
c_wRegister5_init when "000001",
c_wRegister11_init when "000011",
X"00000000" when OTHERS;
with p_mux_SWsel select
p_wRegister4_init <=
c_wRegister12_init when "000011",
X"00000000" when OTHERS;
with p_mux_SWsel select
p_wRegister5_init <=
c_wRegister13_init when "000011",
X"00000000" when OTHERS;
p_wRegister6_init <= X"00000000";
p_wRegister7_init <= X"00000000";
p_wRegister8_init <= X"00000000";
p_wRegister9_init <= X"00000000";
p_wRegister10_init <= X"00000000";
p_wRegister11_init <= X"00000000";
p_wRegister12_init <= X"00000000";
p_wRegister13_init <= X"00000000";
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Read mux
with p_mux_SWsel select
p_rRegister0 <=
......@@ -230,13 +308,13 @@ architecture rtl_cPCI_registerMux of cPCI_registerMux is
with p_mux_SWsel select
p_rRegister2 <=
p_mux_rRegister4 when "000001",
p_mux_rRegister4 when "000001",
p_mux_rRegister10 when "000011",
X"00000000" when OTHERS;
with p_mux_SWsel select
p_rRegister3 <=
p_mux_rRegister5 when "000001",
p_mux_rRegister5 when "000001",
p_mux_rRegister11 when "000011",
X"00000000" when OTHERS;
......@@ -250,8 +328,6 @@ architecture rtl_cPCI_registerMux of cPCI_registerMux is
p_mux_rRegister13 when "000011",
X"00000000" when OTHERS;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
p_rRegister6 <= X"00000000";
p_rRegister7 <= X"00000000";
p_rRegister8 <= X"00000000";
......@@ -261,5 +337,108 @@ architecture rtl_cPCI_registerMux of cPCI_registerMux is
p_rRegister12 <= X"00000000";
p_rRegister13 <= X"00000000";
------------------------------------------------------------------------------
------------------------------------------------------------------------------
p_csw(0) <= p_mux_csw(0); -- cmd register
-- Duplication write strobe mux
with p_mux_SWsel select
p_csw(1) <=
p_mux_csw(1) when "000000",
'0' when OTHERS;
with p_mux_SWsel select
p_csw(2) <=
p_mux_csw(2) when "000000",
'0' when OTHERS;
-- Top-up write strobe mux
with p_mux_SWsel select
p_csw(3) <=
p_mux_csw(1) when "000001",
'0' when OTHERS;
with p_mux_SWsel select
p_csw(4) <=
p_mux_csw(2) when "000001",
'0' when OTHERS;
with p_mux_SWsel select
p_csw(5) <=
p_mux_csw(3) when "000001",
'0' when OTHERS;
with p_mux_SWsel select
p_csw(6) <=
p_mux_csw(4) when "000001",
'0' when OTHERS;
-- LINAC multipulse write strobe mux
with p_mux_SWsel select
p_csw(7) <=
p_mux_csw(1) when "000010",
'0' when OTHERS;
with p_mux_SWsel select
p_csw(8) <=
p_mux_csw(2) when "000010",
'0' when OTHERS;
-- LINAC monitoring write strobe mux
with p_mux_SWsel select
p_csw(9) <=
p_mux_csw(1) when "000011",
'0' when OTHERS;
with p_mux_SWsel select
p_csw(10) <=
p_mux_csw(2) when "000011",
'0' when OTHERS;
with p_mux_SWsel select
p_csw(11) <=
p_mux_csw(3) when "000011",
'0' when OTHERS;
with p_mux_SWsel select
p_csw(12) <=
p_mux_csw(4) when "000011",
'0' when OTHERS;
with p_mux_SWsel select
p_csw(13) <=
p_mux_csw(5) when "000011",
'0' when OTHERS;
with p_mux_SWsel select
p_csw(14) <=
p_mux_csw(6) when "000011",
'0' when OTHERS;
p_csw(15) <= p_mux_csw(15);
------------------------------------------------------------------------------
------------------------------------------------------------------------------
p_csr(1) <= p_mux_csr(1);
p_csr(2) <= p_mux_csr(2);
p_csr(3) <= p_mux_csr(3);
p_csr(4) <= p_mux_csr(4);
p_csr(5) <= p_mux_csr(5);
p_csr(6) <= p_mux_csr(6);
p_csr(7) <= p_mux_csr(7);
p_csr(8) <= p_mux_csr(8);
p_csr(9) <= p_mux_csr(9);
p_csr(10) <= p_mux_csr(10);
p_csr(11) <= p_mux_csr(11);
p_csr(12) <= p_mux_csr(12);
p_csr(13) <= p_mux_csr(13);
p_csr(14) <= p_mux_csr(14);
p_csr(15) <= p_mux_csr(15);
------------------------------------------------------------------------------
------------------------------------------------------------------------------
end architecture rtl_cPCI_registerMux;
fpga/sources/src_cPCI/cPCI_statusManager.vhdl
View file @ 1e2013e4
......@@ -9,7 +9,7 @@
-- File : cPCI_statusManager.vhdl
-- Revision : x.x.x
-- Created : December 05, 2012
-- Updated : November 14, 2013
-- Updated : November 18, 2013
-------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -49,7 +49,7 @@ use work.registers_init.all;
-------------------------------------------------------------------------------
entity cPCI_statusManager is
port (
p_inStates : in std_logic_vector (29 downto 0);
p_inStates : in std_logic_vector (8 downto 0);
p_status : out std_logic_vector (29 downto 0);
p_cfgSW : in std_logic_vector (5 downto 0);
p_clk60MHz : in std_logic;
......@@ -68,7 +68,7 @@ architecture rtl_cPCI_statusManager of cPCI_statusManager is
-----------------------------------------------------------------------------
-- signal
-----------------------------------------------------------------------------
signal s_status : std_logic_vector (29 downto 0);
signal s_status : std_logic_vector (8 downto 0);
-----------------------------------------------------------------------------
-- Components
......@@ -85,22 +85,18 @@ architecture rtl_cPCI_statusManager of cPCI_statusManager is
s_status <= c_status_reg_init;
elsif (falling_edge(p_clk60MHz)) then
case p_cfgSW is
when "000000" => s_status <= p_inStates and c_cfgSW_mask0;
when "000001" => s_status <= p_inStates and c_cfgSW_mask1;
when "000010" => s_status <= p_inStates and c_cfgSW_mask2;
when "000011" => s_status <= p_inStates and c_cfgSW_mask3;
when "000100" => s_status <= p_inStates and c_cfgSW_mask4;
when "000101" => s_status <= p_inStates and c_cfgSW_mask5;
when "000110" => s_status <= p_inStates and c_cfgSW_mask6;
when "000111" => s_status <= p_inStates and c_cfgSW_mask7;
when others => s_status <= p_inStates;
when "000000" => s_status <= "00000000" & p_inStates(0);
when "000001" => s_status <= "000000" & p_inStates(3 downto 1);
when "000010" => s_status <= "00000000" & p_inStates(4);
when "000011" => s_status <= "000000" & p_inStates(8 downto 6);
when others => s_status <= "000000000";
end case;
end if;
end process;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
p_status <= s_status;
p_status <= "000000000000000000000" & s_status;
end architecture rtl_cPCI_statusManager;
fpga/sources/top.vhdl
View file @ 1e2013e4
......@@ -7,7 +7,7 @@
-- File : top.vhd
-- Revision : x.x.x
-- Created : October 26, 2012
-- Updated : November 18, 2013
-- Updated : November 27, 2013
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -139,6 +139,21 @@ architecture rtl_top of top is
signal s_wRegister12 : std_logic_vector (31 downto 0);
signal s_wRegister13 : std_logic_vector (31 downto 0);
signal s_wRegister0_init : std_logic_vector (31 downto 0);
signal s_wRegister1_init : std_logic_vector (31 downto 0);
signal s_wRegister2_init : std_logic_vector (31 downto 0);
signal s_wRegister3_init : std_logic_vector (31 downto 0);
signal s_wRegister4_init : std_logic_vector (31 downto 0);
signal s_wRegister5_init : std_logic_vector (31 downto 0);
signal s_wRegister6_init : std_logic_vector (31 downto 0);
signal s_wRegister7_init : std_logic_vector (31 downto 0);
signal s_wRegister8_init : std_logic_vector (31 downto 0);
signal s_wRegister9_init : std_logic_vector (31 downto 0);
signal s_wRegister10_init : std_logic_vector (31 downto 0);
signal s_wRegister11_init : std_logic_vector (31 downto 0);
signal s_wRegister12_init : std_logic_vector (31 downto 0);
signal s_wRegister13_init : std_logic_vector (31 downto 0);
signal s_rRegister0 : std_logic_vector (31 downto 0);
signal s_rRegister1 : std_logic_vector (31 downto 0);
signal s_rRegister2 : std_logic_vector (31 downto 0);
......@@ -160,8 +175,10 @@ architecture rtl_top of top is
signal s_wRegister_foo10 : std_logic_vector (31 downto 0);
signal s_wRegister_foo12 : std_logic_vector (31 downto 0);
signal s_csw : std_logic_vector (14 downto 0); -- chip select of internal write transfert
signal s_csr : std_logic_vector (14 downto 0); -- chip select of internal read transfert
signal s_csw : std_logic_vector (15 downto 0); -- chip select of internal write transfert
signal s_csr : std_logic_vector (15 downto 0); -- chip select of internal read transfert
signal s_mux_csw : std_logic_vector (15 downto 0);
signal s_mux_csr : std_logic_vector (15 downto 0);
signal s_clk60MHz : std_logic; -- 60 MHz clock
signal s_clk1kHz : std_logic; -- 1 kHz clock
signal s_clk500mhz : std_logic; -- 0.5 Hz clock
......@@ -283,6 +300,21 @@ architecture rtl_top of top is
p_wRegister11 => s_wRegister11,
p_wRegister12 => s_wRegister12,
p_wRegister13 => s_wRegister13,
-- Write registers init values
p_wRegister0_init => s_wRegister0_init,
p_wRegister1_init => s_wRegister1_init,
p_wRegister2_init => s_wRegister2_init,
p_wRegister3_init => s_wRegister3_init,
p_wRegister4_init => s_wRegister4_init,
p_wRegister5_init => s_wRegister5_init,
p_wRegister6_init => s_wRegister6_init,
p_wRegister7_init => s_wRegister7_init,
p_wRegister8_init => s_wRegister8_init,
p_wRegister9_init => s_wRegister9_init,
p_wRegister10_init => s_wRegister10_init,
p_wRegister11_init => s_wRegister11_init,
p_wRegister12_init => s_wRegister12_init,
p_wRegister13_init => s_wRegister13_init,
-- Read registers
p_rRegister0 => s_rRegister0,
p_rRegister1 => s_rRegister1,
......@@ -299,8 +331,8 @@ architecture rtl_top of top is
p_rRegister12 => s_rRegister12,
p_rRegister13 => s_rRegister13,
-- Internal bus
p_CSW => s_csw, -- chip select of internal write transfert
p_CSR => s_csr, -- chip select of internal read transfert
p_CSW => s_mux_csw, -- chip select of internal write transfert
p_CSR => s_mux_csr, -- chip select of internal read transfert
-- Other signals
p_reset => s_reset -- reset
);
......@@ -312,20 +344,24 @@ architecture rtl_top of top is
-- 3 : 0x0C : config register (R)
-- 4 : 0x10 : status register (R/W)
-- 5 : 0x14 : command register (R/W)
-- Duplication
-- 6 : 0x18 : time between two synchronization pulses (R) [duplication mode]
-- 7 : 0x1C : maximum delay before a missing synchro pulse is signaled (R/W) [duplication mode]
-- 8 : 0x20 : beam lost hold off time (R/W) [top-up]
-- 9 : 0x24 : beam lost hold on time (R/W) [top-up mode]
-- 10 : 0x28 : gating hold off time (R/W) [top-up mode]
-- 11 : 0x2C : gating window time (R/W) [top-up mode]
-- 12 : 0x30 : time between two synchronization pulses (R) [LINAC multipulse mode]
-- 13 : 0x34 : maximum delay before a missing synchro pulse is signaled (R/W) [LINAC multipulse mode]
-- 14 : 0x38 : time between two SPM pulses (R) [LINAC monotiring mode]
-- 15 : 0x3C : maximum delay before a missing SPM is signaled (R/W) [LINAC monitoting mode]
-- 16 : 0x40 : time between two LPM pulses (R) [LINAC monotiring mode]
-- 17 : 0x44 : maximum delay before a missing SPM is signaled (R/W) [LINAC monitoting mode]
-- 18 : 0x48 : number of simultaneous SPM / LPM pulses (R) [LINAC monitoting mode]
-- 19 : 0x4C : reset the simultaneous SPM / LPM counter (W) [LINAC monitoting mode]
-- Top-up
-- 8 : 0x18 : beam lost hold off time (R/W) [top-up]
-- 9 : 0x1C : beam lost hold on time (R/W) [top-up mode]
-- 10 : 0x20 : gating hold off time (R/W) [top-up mode]
-- 11 : 0x24 : gating window time (R/W) [top-up mode]
-- LINAC multipulse
-- 12 : 0x18 : time between two synchronization pulses (R) [LINAC multipulse mode]
-- 13 : 0x1C : maximum delay before a missing synchro pulse is signaled (R/W) [LINAC multipulse mode]
-- LINAC monitoring
-- 14 : 0x18 : time between two SPM pulses (R) [LINAC monitiring mode]
-- 15 : 0x1C : maximum delay before a missing SPM is signaled (R/W) [LINAC monitoting mode]
-- 16 : 0x20 : time between two LPM pulses (R) [LINAC monitiring mode]
-- 17 : 0x24 : maximum delay before a missing SPM is signaled (R/W) [LINAC monitoting mode]
-- 18 : 0x28 : number of simultaneous SPM / LPM pulses (R) [LINAC monitoting mode]
-- 19 : 0x30 : reset the simultaneous SPM / LPM counter (W) [LINAC monitoting mode]
cPCI_registerMUX : entity work.cPCI_registerMUX (rtl_cPCI_registerMUX)
port map (
-- Write register
......@@ -374,7 +410,7 @@ architecture rtl_top of top is
p_mux_rRegister13 => s_linacMONsimTriggRST, -- not used ; write only register
-- (reset the s_linacMONsimTrigg register)
-- Mux registers
-- Write registers
p_wRegister0 => s_wRegister0,
p_wRegister1 => s_wRegister1,
p_wRegister2 => s_wRegister2,
......@@ -389,6 +425,23 @@ architecture rtl_top of top is
p_wRegister11 => s_wRegister11,
p_wRegister12 => s_wRegister12,
p_wRegister13 => s_wRegister13,
-- Write registers init
p_wRegister0_init => s_wRegister0_init,
p_wRegister1_init => s_wRegister1_init,
p_wRegister2_init => s_wRegister2_init,
p_wRegister3_init => s_wRegister3_init,
p_wRegister4_init => s_wRegister4_init,
p_wRegister5_init => s_wRegister5_init,
p_wRegister6_init => s_wRegister6_init,
p_wRegister7_init => s_wRegister7_init,
p_wRegister8_init => s_wRegister8_init,
p_wRegister9_init => s_wRegister9_init,
p_wRegister10_init => s_wRegister10_init,
p_wRegister11_init => s_wRegister11_init,
p_wRegister12_init => s_wRegister12_init,
p_wRegister13_init => s_wRegister13_init,
-- Read registers
p_rRegister0 => s_rRegister0,
p_rRegister1 => s_rRegister1,
......@@ -405,6 +458,11 @@ architecture rtl_top of top is
p_rRegister12 => s_rRegister12,
p_rRegister13 => s_rRegister13,
p_mux_csw => s_mux_csw,
p_mux_csr => s_mux_csr,
p_csw => s_csw, -- chip select of internal write transfert
p_csr => s_csr, -- chip select of internal read transfert
-- Other signals
p_mux_SWsel => pin_SW -- configuration switch (duplication, top-up, etc.)
);
......@@ -430,7 +488,6 @@ architecture rtl_top of top is
p_inStates(6) => s_linacMONdelayError(0), -- time between 2 SPM exceeded the maximum delay
p_inStates(7) => s_linacMONdelayError(1), -- time between 2 LPM exceeded the maximum delay
p_inStates(8) => s_linacMONLED(0), -- simultaneous SPM / LPM
p_inStates(29 downto 9) => "000000000000000000000", -- not used
p_status => s_status,
p_cfgSW => pin_SW, -- configuration switch (duplication, top-up, etc.)
-- Other signals
......
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