Frequently Asked Questions
Design
Q: Is the ISERDES also available on the HR pins?
A: Yes.
Q: My SPEC7 doesn't power-up; only LED D23 is lit.
A 1: SPEC7 contains a 12V to 3V3 10Amp DC-DC Step-Down Converter (N2 Intel EN29A0QI) that has an Under Voltage Lock Out (ULVO) protection. Circuit protection only allows the DC-DC Converter to start when the input voltage is below the UVLO threshold. In the case where the power supply is switched off and on again to fast (for example < 5 seconds) then the bulk capacitance in your power supply may still keep the SPEC7 input voltage above the UVLO thershold, hence preventing the DC/DC converter to start.
S 1: Allow enough time for the input voltage to get below the UVLO thershold.
A 2: When a DIO card is plugged onto SPEC7 then, due to a DIO card issue, an input signals on the DIO can keep the voltage on the SPEC7 12V line above the UVLO thershold, preventing the DC-DC convertor to start.
S 2: If a DIO card is plugged onto SPEC7 then remove the input signals before power-up.
Q: Why do I get an error "no device detected on target" when using my Xilinx JTAG download cable?
A: SPEC7 switches its JTAG chain between FPGA and Xilinx download cable based on the status of pin 1 of the programmer (see figure 5 of the SPEC7 documentation and/or the schematics sheet 26, J9). Pin 1 is floating on Xilinx Platform Cable USB II (see figure 14) or on the adapter of Digilent JTAG-HS2 hence the JTAG chain on the SPEC7 keeps selecting the default FPGA JTAG pins instead of selecting the download cable JTAG pins.
Solution:
You can ground pin 1 by adding a blob of solder between pins 1 and 3 of the download cable connector, see picture below:
Cables that do have pin 1 connected are: Xilinx Platform USB and Digilent XUP USB-JTAG programming Cable, both referring to the same datasheet (see figure 17).
Q: Could I make a cheaper version using the Z030 instead of the Z035?
A: Originally the design was made to be equipped with a Z030 as well as with a Z035(/Z045) FPGA. But then it is not possible to use the QPLL for the WR GTX as a Z030 device only has one QUAD (GTX112) with a single QPLL which is occupied by the PCIe endpoint (see also: SPEC7v2_CPLL_QPLL.pdf)
Therefore we had to swap the WR and FMC reference clocks such that the QPLL in GTX111 (present in Z035 but not in Z030) can be used for the WR reference clock. See Issue #22 (closed).
Possibly applications not needing WR could still use a Z030. Then again, because the Z035 is used more often, possibly the quantity pricing that the producers have for that type may be even cheaper than for the Z030.
Gateware compilation
Q: Can I use the free WebPack software?
A: Yes, when the a XC7Z030 is assembled on the board. The Z035 and Z045 are not supported. See on the Xilinx site: Vivado Design Suite Evaluation and WebPACK.
Q: Is partial reconfiguration also available on the WebPack software?
A: No. However, the Partial Reconfiguration feature is also available
for purchase for WebPack
additions.
For example, partial reconfiguration is needed when the SPEC7 needs to
be reconfigured over the PCIe bus.
25 August 2021