SPEC7 v2 QPLL / CPLL use
It is expected (and under study for the Zynq-7000 devices) that GTX transceiver QPLL phase noise will be lower than CPLL phase noise. For SPEC7 low phase noise is a key aspect. However free choice of transceiver PLL is limited for SPEC7 v2.
This is due to the fact that SPEC7 was designed such that it can be equipped with a Z030 as well as with a Z035(/Z045) FPGA. It is not possible to use the QPLL for the WR GTX. A Z030 device only has one QUAD (GTX112) with a single QPLL which is occupied by the PCIe endpoint (see also: SPEC7v2_CPLL_QPLL.pdf)
It is recommended to use Z035 for future revisions of SPEC7 and swap the WR and FMC reference clocks such that the QPLL in GTX111 (present in Z035 but not in Z030) can be used for the WR reference clock.