Q: Why do I get an error "no device detected on target" when using my Xilinx JTAG download cable?
A: SPEC7 switches its JTAG chain between FPGA and Xilinx download cable based on the status of pin 1 of the programmer (see figure 5 of the SPEC7 documentation and/or the schematics sheet 26, J9).
Pin 1 is floating on Xilinx Platform Cable USB II (see figure 14) or on the adapter of Digilent JTAG-HS2 hence the JTAG chain on the SPEC7 keeps selecting the default FPGA JTAG pins instead of selecting the download cable JTAG pins.
You can ground pin 1 by adding a blob of solder between pins 1 and 3 of the download cable connector, see picture below:
Cables that do have pin 1 connected are: Xilinx Platform USB and Digilent XUP USB-JTAG programming Cable, both referring to the same datasheet (see figure 17).
Q: Could I make a cheaper version using the Z030 instead of the Z035?
A: Originally the design was made to be equipped with a Z030 as well as with a Z035(/Z045) FPGA. But then it is not possible to use the QPLL for the WR GTX as a Z030 device only has one QUAD (GTX112) with a single QPLL which is occupied by the PCIe endpoint (see also: SPEC7v2_CPLL_QPLL.pdf)
Therefore we had to swap the WR and FMC reference clocks such that the QPLL in GTX111 (present in Z035 but not in Z030) can be used for the WR reference clock. See Issue #22 (closed).
Possibly applications not needing WR could still use a Z030. Then again, because the Z035 is used more often, possibly the quantity pricing that the producers have for that type may be even cheaper than for the Z030.