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SPEC7
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Cycle Analytics
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PUDC_B is floating. not allowed.
#20
· opened
May 29, 2020
by
Guido Visser
0
updated
May 29, 2020
Route BE_REFCLK_P/N input back to outout on the bullseye
#19
· opened
May 27, 2020
by
Guido Visser
0
updated
May 27, 2020
Soft start 3V3_FMC
#18
· opened
May 17, 2020
by
Peter Jansweijer
0
updated
Jul 01, 2020
LTC6950 dissipation
#17
· opened
May 17, 2020
by
Peter Jansweijer
0
updated
May 17, 2020
ESD protection CP2105 (U54, dual UART)
#16
· opened
May 17, 2020
by
Peter Jansweijer
0
updated
May 17, 2020
"Soft" reset to FPGA
#15
· opened
Mar 19, 2020
by
Peter Jansweijer
0
updated
Mar 19, 2020
BullsEye SPARE_P/N outputs always disabled
#14
· opened
Feb 25, 2020
by
Peter Jansweijer
0
updated
Feb 25, 2020
PPS_OUT wrongly reclocked when BE_REFCLK is used as 125 MHz refclk (using HPSEC)
#13
· opened
Feb 24, 2020
by
Peter Jansweijer
1
updated
Feb 24, 2020
SPEC7 V2: BFT92 (T14 and T15) obsolete
#12
· opened
Feb 24, 2020
by
Peter Jansweijer
0
updated
Feb 24, 2020
