Simple PCIe FMC carrier (SPEC)
Project description
The FMC PCIe Carrier is an FMC carrier that can hold one FMC card and an SFP connector. On the PCIe side it has a 4-lane interface, while the FMC mezzanine slot uses a low-pin count connector. This board is optimised for cost and will be usable with most of the FMC cards designed within the OHR project (e.g. ADC cards, Fine Delay). For boards needing more possibilities (e.g. programmable clock resources, fast SRAM, fast interconnect between carriers), the FMC PCIe Carrier or its VME counter part can be used.
Other FMC projects and the FMC standard are described in FMC Projects.
SPEC_under_design.bmp
Image of PCB under design.*
Main Features
* 4-lane PCIe (Gennum GN4124)
* FMC slot with low pin count (LPC) connector
o Vadj fixed to 2.5V
o No dedicated clock signals from Carrier to FMC (only available on HPC
pins)
o LPC cheaper than HPC and also easier to mount
o FMC connectivity: all 34 differential pairs connected, 1 GTP
transceiver with clock, 2 clock pairs, JTAG
* 1 Spartan6 FPGA (XC6SLX45T)
* Simple clocking resources
o 1 10-280 MHz Programmable XO Oscillator (Silicon Labs Si570)
o 2 25 MHz TCXOs controlled by a DAC
o 1 low-jitter frequency synthesizer (TI CDCM61004)
* On board memory
o A 2Gbit DDR3
o 1 SPI 128Mbit flash PROM for multiboot FPGA powerup configuration,
storage of the FPGA firmware or of critical data
* Front panel containing
o 1 Small Formfactor Pluggable (SFP) cage for fibre-optic transceiver
(WhiteRabbit support)
o Programmable LED
o FMC front panel
* Internal connectors
o 1 JTAG header for Xilinx programming during debugging
o 1 or 2 SATA connectors if don't add much cost
* FPGA configuration. The FPGA can optionally be programmed from:
o GN4124 SPRIO interface (loaded by software driver at startup)
o JTAG header
o SPI 128Mbit flash PROM
o selectable by assembly of 0 Ohm resistors. Default option would be
loading via the GN4124 at driver startup.
* Optimised for cost
Detailed project information
CERN LHC Equipment name: CFEIA
Status
| Date | Event |
| 22-06-2010 | Start of project. Design will be done by an external company, based on the FMC PCIe Carrier. Reviewing will be done by CERN. |
| 29-06-2010 | Main features reviewed by JS, PA, MC & EB. Design can start. |
| 12-07-2010 | First schematics published. Ready for review. |
| 16-07-2010 | First review held. Considered as a preliminary review as schematics not finished. |
| 24-07-2010 | Second version schematics published. |
| 03-08-2010 | Second schematics review held. FMC to Xilinx bank connections not correct. Clock missing. Supply Xilinx wrong. Cleanup required. |
| 03-09-2010 | Schematics corrected. Waiting for a final schematics review from CERN. |
| 07-09-2010 | Third schematics review held. review07092010 |
| 10-09-2010 | Review comments integrated review07092010comments. Start of PCB layout. |
| 21-09-2010 | PCB layout being made. Will fit on a 6-layer board. |
| 27-09-2010 | PCB layout 'ready'. |
| 01-10-2010 | PCB layout modified before review. |
| 04-10-2010 | Preliminary PCB layout review requiring modifications to layout. review04102010 |
| 05-10-2010 | PCB layout review held. review05102010 |
| 08-10-2010 | Order placed for production of three prototypes. |
Erik van der Bij - 8 October 2010
