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Simple PCIe FMC carrier SPEC

Review05102010

Last edited by Erik van der Bij
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Review05102010

PCB layout review held on 5 October 2010

Present: P. Alvarez Sanchez, M. Cattin, T. Wlostowski, E.van der Bij

Files used for the review:
https://www.ohwr.org/project/spec/tree/15/trunk/circuit_board/SimplePCIeFMCCarrier/PCB-Layout

The following is a compilation of the e-mail exchanges of the review.

  • there shouldn't be any power/ground plane on the PCIe tongue (remove the copper from under the contacts)
  • clk0_m2c_p/n - it should be a global clock line
    • you wrote recently: "m2c_clkx and can be connected to any other bank. "
    • I can connect it to bank0.
  • make sure there's a solder mask over all vias
    This I missed during last corrections, before I applied it to all of them.
  • LA17_CC, LA18_CC should be connected to a global clock
    • I have to check it, didn't you told last time about LA16 and LA17?
  • resistance divider for GCLK16/17 (pseudo-differential input for CLK25_VCXO)
    • Ok, there is already 22R resistor, but I will add real divider.
      • Pablo: This is to divide the 3V3 and connect it as a VREF to the unused GCLK16/17 (I do not have the schematic on my eyes sorry) . The excursion on the IVT oscillator can sometimes be very low (only 0.8V), so I think in case we ever mount this option it is better to use it as pseudo LVDS.
  • single ground plane (no cuts)
    • Grzeg: I know exactly why I added the cut. It is to limit current propagation around the board. The input and coil AC current caused by switching should enclose as close as possible to the DC/DC converter. The cuts make sure that these current loops are local and do not propagate around the PCB. I saw this idea in many reference designs i.e. 4-layer main boards.
      • Erik: We didn't feel very strongly about this, but we liked to remove it anyway. But as I'd like to have the board as simple as possible and use tricks only when really needed, please remove these cuts and have a solid ground plane. I take the responsibility if it doesn't work because of that.
        Reasoning:
        • Simpler gives less troubles in most cases. So only make more complicated when absolutely needed.
        • The design will be easier to understand (useful for open designs).
        • _our direct experience: the fast ADC FMC board has a DC/DC and uses solid ground planes and has an excellent good SNR. This also has been verified with an analog specialist**. And this all on a very dense and small card. The SPEC is digital so should have no problems at all._**: "I think that just having a good solid GND plane everywhere will give best results overall (or maybe 2 GND planes if you have enough PCB layers)."
  • remove the 1.00 mm dimension from L5
    • OK
  • you can reverse polarities for PER pairs
    • OK
  • cleanup (acute angle trace - pad connections in few places)
    • in case of coils I did it on purpose
  • remove EDA number from the silkscreen
    • OK
  • remove "Cagebot" , "CageTop" from the SFP
    • OK
  • put CERN logo somewhere and a big name "SPEC"
    • OK
  • put boxes with layer numbers on the PCB area
    • OK
  • put "JTAG" text next to JTAG connector
    • OK
  • clk1_m2c_p/n should be connected to a gclk too. Suggest to use Bank 1.
  • The lines on Layer 3 and Layer 4 sometimes are precisely above each other. Yes we know, there is 1mm distance, but as it is prepreg it is not precise. Furthermore there is enough space on each layer, so can you please tear them somewhat apart so that they are not above each other anymore?
    • OK
  • PCIe spec: total thickness 1.57 +/- 0.06 mm. The board actually is 1.47mm. Can you make that it becomes 1.57?
    • OK
  • Add the LHC name "CFCKA"
    • may be wrong actually

Erik van der Bij - 8 October 2010