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Simple PCIe FMC carrier SPEC

Review07092010comments

Last edited by Erik van der Bij
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Review07092010comments

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PCB review held on 7 September 2010

Present: M.Cattin, T.Wlostwski, E.van der Bij

Files used for the review: https://www.ohwr.org/project/spec/tree/8/trunk/circuit_board/SimplePCIeFMCCarrier/Schematics

General

  • There are many components in 0402 package, also some resistors. Please use these only where absolutely necessary, in my opinion only under a BGA. Do not combine 100nF capacitors of 0402 and 0603 combined to prevent oscillation or so.
    • most of them are in 0402 in order to decrease number of different components. Since we use termination resistors in 0402 close for SDRAM termination, it was logical to use other resistors with same value in same package.
    • I changed all to 0603. Only DDR3 and Gennum termination ones are 0402. Since there are no series termination resistors, 22R ones could be also used in 0603 package.
  • Fill in correctly the names in the name block (your name in full, initials of the three of us here). Do this on all pages. Also fill in the XX/XX/XXXX
    • OK, done
  • In name block: SImple -> Simple. Also on a few other pages. Check these all.
    • OK, done
  • All unconnected pins should be marked as No DRC (with a cross).
    • I'll have to look ones again carefully.
    • I marked all as NoDRC, but I think that only unused Inputs and I/O pins need to be marked. ERC does not care about disconnected output pins. Of course if one set it to check it will care :)
  • Can you generate a full BOM to verify the quantity of components?
    • I did id already and decreased number of different components significantly. That's why there are some resistors connected in series. But I did it a few revisions ago and will do it again.
    • I optimised BOM - unified component footprints and values.

Page 1

  • GN4124_GPIO/TDI/TDO/TMS/TCK should not be bidirectional.
    • OK, fixed

Page 2

  • R254 -> No should be YES as it enables the LVDS outputs (please check).
    • assembled R254 will set OS0 thus enabling LVPECL mode. Instead, R253 should be mounted. Fixed
  • move R36 and R255 to input of DAC to make more clear that this is a low-pass filter.
    • OK, fixed, we are talking about DAC OUTPUT
  • remove text Project/Equipment under C9.
    • OK
  • R238 in 0402 package -> make 0603 or larger.
    • But this will increase number of components, I can also try to fit 0603s under BGA
    • done

Page 3

  • Note on the left: "no skew/as low as possible". Please relax these requirements a bit. The skew between various LA pairs may be 200 ps. See Observation 5.10 and table 4 of the FMC spec.
  • Mark the connectors with a large letter H, G, D & C (I know it is in the pin names, but J4C is actualy row G.
    • OK, done
  • Possibly have 3 decoupling C's near P3V3_FMC on row D.
    • OK, added 100nF to make it similar to other voltages

Page 4

  • Move note "Calibration resistor" to R188.
    • OK
  • Note at the bottom: capictor -> capacitor.
    • I simply copied from original ),), fixed.
  • There is a mix of 0402 and 0603 C for same purpose.
    • OK, I will unify 100nF caps in signal traces. 0402 are recommended because they to not disturb high speed trace impedance so much.

Page 5

  • Remove the 16V marking of the capacitors, it makes these two look special.
    • OK, but in case of caps used at 12V I will display voltage information

Page 6

  • Top-left note: supplid -> supplied, utputs -> outputs.
    • done
  • signal on G11 not used, remove line.
    • done

Page 7

  • No comments.

Page 8

  • Connector at top-left: should be a 2mm pitch type. It is not now.
    • I already changed it, Tom noticed wrong footprint on PCB
  • DIR of IC7 should be 2V5 (as is referenced to VCCA and also easier for layout).
    • OK, it's 3.3V compatible but changed it.
  • 2V5_CCLK should have bidir flag.
    • OK, done
  • The memory can be smaller for cost reasons 16 MByte is too expensive for a 2 MByte programming file. If possible, change the symbol now so that the BOM will take this into account.
    • changed to M25P32-VMF6G which costs <2$
  • Note in middle of page: ouputs-> outputs, anythink-> anything, reistor-> resistor.
    • OK, done
  • Note at bottom-left (SPI_CLK 50 Ohm): remove.
    • OK, in this case 5mils track would do ~50Ohm anyway:) But this makes no difference since we do not have termination.
  • Mark in note on left that "2) Slave serial" is the default mode.
    • OK,done

Page 9

  • P3V3_GN4124 (4 times) does not exist! It is not generated anywhere. I assume it should be connected to P3V3. Verify if this voltage is not used on any other pages.
    • OK, fixed, it should be P3V3
  • Line TRST connected to IC15E, has a cross in it.
    • OK, fixed
  • OSC3: the parttype is not defined.
    • it is, but it was not displayed: MCOT7250005V00000RA, also enabled part types for other oscillators
  • Remove the 22 Ohm series termination resistors coming from IC15B. This will help layout. We believe that the parallel terminations of 51 Ohm are good enough. In fact having both parallel and series termination is no good as the series termination creates only half the swing and needs the reflection at the end of the line to make it a full swing at the input.
    • this I already did. I was wander why both terminations were used.
  • Remove the 22 Ohm series termination resistors coming from IC15A.
  • In textblock at bottom, the left line is missing.
    • it seems to be a printing issue, on schematic it looks fine

Page 10

  • C314 is 22 uF in 0805 package. This should be different (1206 is used on page 12).
    • I know, there are some used in 12V chain with 1206 footprint, I will unify the values.
    • all changed to 0805
    • Correction: after discussion, will be changed to 1206 type: lower ESR and cheaper.
  • In the Gennum Gullwing reference design, pin E4 (PE_MODE) has a 4k7 pulldown and a jumper to 3V3. This pin has the function as described in Note 1 below.
    • there is no trace of this functionality in the datasheet. I placed not mounted 0R resistor between E4 pin and P3V3
      The reference design does have this same pulldown and switch for G6, D4, C4 (named OCT_EN0/1/2). I don't know the function and could quickly find it and asked Gennum now. In CERN's symbol it is marked as VSS...
    • the same as in the datasheet
  • There was a note from Gennum when reviewing the PFC design. I'm not sure if is taken into account for the PFC, but Gennum believes it is important:
    L2P Dframe, valid and clkp, should have 10K pull downs. These pulldowns drive the control signals to a known level when the FPGA is not driving them. There have been cases at the time FPGA is removed from reset that garbage data gets clocked into the fifo. This is not on the Gullwing 4124 ref design but it is present on the Altera GN4121 ref design. This is an important one to do.
    • I added 10k pull down to the L2P_DFRAME and L2P_CLK_P lines

Page 11

  • Replace the 3 fuses by 3Amp version as the FMC spec allows to draw 3Amp on 3V3. Just 1A on 12V, but have there also a 3Amp fuse to simplify the BOM.
    • OK, done
  • Text block: Liear-> Linear.
    • done

Page 12

  • The Layout notes are rather generic (e.g. signal/power ground). We'll ignore some of the notes.
    • I simply copied them from the datahseet, removed the most obvious ones.

Page 13

  • Move the Cage Top and Bottom symbols so that they are in the drawing on top of the other symbol. There seems to be some mix now.
    • for me it seems to be very similar as it is in Pablo design
  • IC14 and IC18: Add No (not mounted). Make sure that the lines to the inputs are very very short.
    • I added a note

Page 14:

  • No comments.

Page 15

  • R155: Add No (not mounted) as by default is 4 lane.
    • OK, done
  • Add a note that it should be possible to cut off a piece of the edge connector to become a x1 board. This means that there should be no power/gnd planes in the x4 area.
    • I added a note

Page 15

  • You may invert the PCIe polarity as is compensated by training. See Note 2.
    • added a note

Page 16

  • Some signals have no name. Remove these.
    • Done

Note 1:
From a mail from Gennum:
"We have a switch on SW6 (position 5) called PE_BODE (is suppose to say PE Mode but someone must have had a cold that day!). That is for forcing PCIe x1 or x4. In the off position it is x4 on it is x1. Most systems that will force x1 mode when inserted in a x4 slot. This will not change the resistive termination but will block any response on lanes above lane 0.
There are some non compliant motherboards which only pay attention to the receiver detect pulse only. At Power up the host sends a pulse on the lane to do what is called receiver detect. It is a primitive TDR method of determining presence of a receiver. In this case is a lane is seen as present and doesn't respond the link should train down. Some motherboards will think there is an error and shut of the slot entirely. This is non PCIe compliant but we have seen some popular motherboards have this issue.
In this case there are 2 solutions. Use a x4 to x1 adapter so there is no mechanical connection of the add-in card fingers to the slot. Or Simpler and cheaper, use masking tape on the edge connector to mask off and make the card a masked x1 card. This applies not only to GN4124 but to GN1406 as well."

Note 2:
The Gennum spec reads:
"The PCI Express receive inputs on the GN4124 (PERp[3:0]/PERn[3:0]) can be connected using either the advertised polarity, or an inverted polarity. Inverted polarity may be chosen in order to simplify the PCB layout by avoiding signal crossover and additional
vias. The GN412x will automatically detect and compensate for polarity inversion during link training. No pin or register settings are required to facilitate this. Polarity may be inverted independently on a per-lane basis as required."

Erik van der Bij, Grzegorz Kasprowicz - 10 September 2010