Simple PCIe FMC carrier (SPEC)
Project description
The FMC PCIe Carrier is an FMC carrier that can hold one FMC card and an SFP connector. On the PCIe side it has a 4-lane interface, while the FMC mezzanine slot uses a low-pin count connector. This board is optimised for cost and is usable with most of the FMC cards designed within the OHR project (e.g. ADC cards, Fine Delay). The board is commercially available.
Labview and Linux drivers are available for the FMC DEL 1ns 4cha delay and FMC TDC 1ns 5cha TDC mezzanine cards.
Boards with a very similar architecture are available for the VME bus
(SVEC - Simple VME FMC Carrier
(SVEC)) and for the PXI
Express bus (SPEXI - Simple PXI express FMC Carrier Board
(SPEXI)).
Other FMC projects and the FMC standard are described in FMC
Projects.
SPEC 1.1 first prototype
Main Features
- 4-lane PCIe (Gennum GN4124) obsolete component, not available anymore
- 1x Xilinx Spartan6 FPGA (XC6SLX45T-3FGG484C) (PCI Device ID: 0x18D)
- special versions with XC6SLX100T and XC6SLX150T available
- FMC slot with low pin count (LPC) connector
- Vadj fixed to 2.5V
- FMC connectivity: all 34 differential pairs connected, 1 GTP transceiver with clock, 2 clock pairs, JTAG, I2C
- No dedicated clock signals from Carrier to FMC (only available on HPC pins)
- Clocking resources
- 1x 10-280 MHz I2C Programmable XO Oscillator, starts up at 100 MHz (Silicon Labs Si570, 570BBC000121DG, freely usable)
- 1x 25 MHz TCXO (MCOT7250003V300000RA) controlled by a DAC with SPI interface (AD5662, used by White Rabbit PTP core)
- 1x 20 MHz VCXO (IQD VCXO026156) controlled by a DAC with SPI interface (AD5662, used by White Rabbit PTP core)
- 1x low-jitter frequency synthesizer (TI CDCM61004, fixed configuration, Fout=125 MHz, used by White Rabbit PTP core)
- On board memory
- 1x 2Gbit (256 MByte) DDR3 (MT41J128M16HA-15E)
- 1x SPI 32Mbit flash PROM for multiboot FPGA powerup configuration, storage of the FPGA firmware or of critical data (M25P32-VMF6P - EOL)
- Miscellaneous
- on-board thermometer IC (DS18B20U+)
- unique 64-bit identifier (DS18B20U+)
- Front panel containing
- 1x Small Formfactor Pluggable (SFP) cage for fibre-optic transceiver (WhiteRabbit support). 1.25 and 2.5 Gbps.
- Programmable Red and Green LEDs
- FMC front panel
- Internal connectors
- 1x JTAG header for Xilinx programming during debugging
- 2x SATA connector
- 1x mini USB AB (USB-UART bridge)
- FPGA configuration. The FPGA can optionally be programmed from:
- GN4124 SPRIO interface (loaded by software driver at startup)
- JTAG header
- SPI 32Mbit flash PROM
- selectable by GN4124 GPIO. Default option would be loading via the SPI flash PROM (stand-alone applications).
- Stand-alone features
- External 12V power supply connector
- mini USB connector
- 4 LEDs
- 2 buttons
- Power consumption: 5-12 Watt, depending on application
- Optimised for cost
- 6-layer PCB
- Optional cooling fan for the mezzanine.
Project information
- Official production documentation: EDMS EDA-02189
- Getting Started with the SPEC (project)
- System architecture
- Users
- Software
- Fan design
- Frequently Asked Questions
Releases
Hardware
- SPEC V4-0
-
SPEC V4-1: same V4-0 base board with additional board supporting a fan
- Only needed in badly ventilated PCs using highly dissipating cards such as the FMC DEL 1ns 4cha
-
SPEC V4-2, SPEC150 with 150T FPGA
SPEC150 project - with larger XC6SLX150T FPGA (PCI Device ID: 0x1A3) and larger FLASH memory (M25P64 instead of M25P32).
Required for certain applications, e.g., when one needs White Rabbit support with the FMCADC100M ADC mezzanine card. Usage of the ADC with the White Rabbit Trigger Distribution project is such a case.
Gateware and Software
| Version | Date | Sources | Binaries |
|---|---|---|---|
| 1.4.4 | 2019-10-29 | Git repository | spec-binaries-v1.4.4.tar.xz |
| 2.0.0 | 2020-07-30 | Git repository | spec-binaries-v2.0.0.tar.xz |
| 2.0.2 | 2020-09-29 | Git repository | spec-binaries-v2.0.2.tar.xz |
Contacts
Commercial producers
- SPEC - Creotech, Poland
- SPEC - INCAA Computers, Netherlands
General questions about project
- Erik van der Bij - CERN
Status
| Date | Event |
|---|---|
| 22-06-2010 | Start of project. Design is done by an external company, based on the FMC PCIe Carrier. Reviewing will be done by CERN. |
| 29-06-2010 | Main features reviewed by JS, PA, MC & EB. Design can start. |
| 12-07-2010 | First schematics published. Ready for review. |
| 10-09-2010 | Review comments integrated. Start of PCB layout. |
| 05-10-2010 | PCB layout review held. |
| 05-11-2010 | Design finished. |
| 19-01-2011 | Three prototypes arrived at CERN. |
| 18-04-2011 | First V1.1 prototypes received, start testing them. |
| 01-07-2011 | Three V2 boards received. One fully tested OK. Two only shortly tested. |
| 17-07-2011 | Order placed for 70 SPEC cards at Seven Solutions. |
| 23-08-2011 | V4 released. Solves a minor mechanical problem with the SFP connector. |
| 14-03-2012 | CERN accepted the 10 preseries boards that were received on 7 March. |
| 12-06-2012 | SPEC boards passed most restrictive EMC tests for industrial and domestic classes. Test report. |
| 13-06-2012 | Board available from three commercial producers. |
| 03-12-2013 | Labview Driver available for FMC DEL 1ns 4cha and FMC TDC 1ns 5cha. |
| 30-03-2015 | Fan design released in EDMS (V4-1). |
| 02-12-2016 | PCIe bridge component (Gennum GN4124) obsolete and not available anymore. A new card should be designed. |
| 11-01-2018 | Start of study of a new design. Contact Erik van der Bij - CERN |
| 19-12-2018 | Over 2000 SPEC boards produced by industry. |
| 19-12-2019 | Created documentation for SPEC150 that has a larger FPGA. |
| 30-07-2020 | SPEC gateware/software v2.0.0 released. |
| 29-09-2020 | SPEC gateware/software v2.0.2 released. |
Erik van der Bij, Matthieu Cattin, Tomasz Wlostowski - 10 February 2022
