There are many components in 0402 package, also some resistors.
Please use these only where absolutely necessary, in my opinion only
under a BGA. Do not combine 100nF capacitors of 0402 and 0603
combined to prevent oscillation or so.
Fill in correctly the names in the name block (your name in full,
initials of the three of us here). Do this on all pages. Also fill
in the XX/XX/XXXX
In name block: SImple -> Simple. Also on a few other pages. Check
All unconnected pins should be marked as No DRC (with a cross).
Can you generate a full BOM to verify the quantity of components?
GN4124_GPIO/TDI/TDO/TMS/TCK should not be bidirectional.
R254 -> No should be YES as it enables the LVDS outputs (please
move R36 and R255 to input of DAC to make more clear that this is a
remove text Project/Equipment under C9.
R238 in 0402 package -> make 0603 or larger.
Note on the left: "no skew/as low as possible". Please relax these
requirements a bit. The skew between various LA pairs may be 200 ps.
See Observation 5.10 and table 4 of the FMC spec.
Mark the connectors with a large letter H, G, D & C (I know it is in
the pin names, but J4C is actualy row G.
Possibly have 3 decoupling C's near P3V3_FMC on row D.
Move note "Calibration resistor" to R188.
Note at the bottom: capictor -> capacitor.
There is a mix of 0402 and 0603 C for same purpose.
Remove the 16V marking of the capacitors, it makes these two look
Connector at top-left: should be a 2mm pitch type. It is not now.
DIR of IC7 should be 2V5 (as is referenced to VCCA and also easier
2V5_CCLK should have bidir flag.
The memory can be smaller for cost reasons 16 MByte is too expensive
for a 2 MByte programming file. If possible, change the symbol now
so that the BOM will take this into account.
Note in middle of page: ouputs-> outputs, anythink -> anything,
Note at bottom-left (SPI_CLK 50 Ohm): remove.
Mark in note on left that "2) Slave serial" is the default mode.
P3V3_GN4124 (4 times) does not exist! It is not generated
anywhere. I assume it should be connected to P3V3. Verify if this
voltage is not used on any other pages.
Line TRST connected to IC15E, has a cross in it.
OSC3: the parttype is not defined.
Remove the 22 Ohm series termination resistors coming from IC15B.
This will help layout. We believe that the parallel terminations of
51 Ohm are good enough. In fact having both parallel and series
termination is no good as the series termination creates only half
the swing and needs the reflection at the end of the line to make it
a full swing at the input.
Remove the 22 Ohm series termination resistors coming from IC15A.
In textblock at bottom, the left line is missing.
C314 is 22 uF in 0805 package. This should be different (1206 is
used on page 12).
In the Gennum Gullwing reference design, pin E4 (PE_MODE) has a 4k7
pulldown and a jumper to 3V3. This pin has the function as described
in Note 1 below.
The reference design does have this same pulldown and switch for G6,
D4, C4 (named OCT_EN0/1/2). I don't know the function and could
quickly find it and asked Gennum now. In CERN's symbol it is marked
There was a note from Gennum when reviewing the PFC design. I'm not
sure if is taken into account for the PFC, but Gennum believes it is
L2P Dframe, valid and clkp, should have 10K pull downs. These
pulldowns drive the control signals to a known level when the FPGA
is not driving them. There have been cases at the time FPGA is
removed from reset that garbage data gets clocked into the fifo.
This is not on the Gullwing 4124 ref design but it is present on the
Altera GN4121 ref design. This is an important one to do.
Replace the 3 fuses by 3Amp version as the FMC spec allows to draw
3Amp on 3V3. Just 1A on 12V, but have there also a 3Amp fuse to
simplify the BOM.
Text block: Liear-> Linear.
The Layout notes are rather generic (e.g. signal/power ground).
We'll ignore some of the notes.
Move the Cage Top and Bottom symbols so that they are in the drawing
on top of the other symbol. There seems to be some mix now.
IC14 and IC18: Add No (not mounted). Make sure that the lines to the
inputs are very very short.
R155: Add No (not mounted) as by default is 4 lane.
Add a note that it should be possible to cut off a piece of the edge
connector to become a x1 board. This means that there should be no
power/gnd planes in the x4 area.
You may invert the PCIe polarity as is compensated by training. See
Some signals have no name. Remove these.
From a mail from Gennum:
"We have a switch on SW6 (position 5) called PE_BODE (is suppose to say
PE Mode but someone must have had a cold that day!). That is for
forcing PCIe x1 or x4. In the off position it is x4 on it is x1. Most
systems that will force x1 mode when inserted in a x4 slot. This will
not change the resistive termination but will block any response on
lanes above lane 0.
There are some non compliant motherboards which only pay attention to
the receiver detect pulse only. At Power up the host sends a pulse on
the lane to do what is called receiver detect. It is a primitive TDR
method of determining presence of a receiver. In this case is a lane is
seen as present and doesn't respond the link should train down. Some
motherboards will think there is an error and shut of the slot entirely.
This is non PCIe compliant but we have seen some popular motherboards
have this issue.
In this case there are 2 solutions. Use a x4 to x1 adapter so there is
no mechanical connection of the add-in card fingers to the slot. Or
Simpler and cheaper, use masking tape on the edge connector to mask off
and make the card a masked x1 card. This applies not only to GN4124 but
to GN1406 as well."
The Gennum spec reads:
"The PCI Express receive inputs on the GN4124 (PERp[3:0]/PERn[3:0])
can be connected using either the advertised polarity, or an inverted
polarity. Inverted polarity may be chosen in order to simplify the PCB
layout by avoiding signal crossover and additional
vias. The GN412x will automatically detect and compensate for polarity
inversion during link training. No pin or register settings are required
to facilitate this. Polarity may be inverted independently on a per-lane
basis as required."