Review04102010
Preliminary PCB layout review held on 1 and 4 October 2010
Present: P. Alvarez Sanchez, E.van der Bij
Files used for the
review:
https://www.ohwr.org/project/spec/tree/14/trunk/circuit_board/SimplePCIeFMCCarrier/PCB-Layout
- The fmc clock lines and they do not follow the convention. LAxx_CC lines should be connected to gclks in bank 0 and m2c_clkx and can be connected to any other bank. See also https://www.ohwr.org/project/fmc-projects/uploads/6737a6f140784d1e9d1ae47ccc003d3e/ClockingFMCs.pdf
- The stackup is not at all clear, which is very risky for the
fabrication. I believe you have wrong names for the layers:
- Top
- L2_Gnd
- L4_Diff -> L3?
- L3_Diff -> L4
- L5_Pwr
- Bott
- Or in the list when you select which layers to show, there is Top (T), L4_diff (1) L3_Diff (3), Bottom (B). Here I don't understand the (1) and (3) either.
- There are many differential pairs that are on top of other pairs. So they couple too much. This is also the case with a Gbit link. Please move them apart.
- There are two 25 MHz clocks that are next to each other over a long distance. Space them apart.
- Remove the DEM/CERN logo. Remove the EDA number. It is not a DEM design.
- C266 and C312 are a bit tight to each other. Space them somewhat more apart so in case we receive somewhat larger ones we can stil mount them.
- Move the '+' signs of the capacitors out of the symbol so that you can see them when the capacitors are mounted.
- Schematic with the FMC connector: align the connector 'flags' with the signal names.
- The pdf file of the layout is not up to date.
Erik van der Bij - 4 October 2010