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Simple PCIe FMC carrier SPEC

Sysarch

Last edited by Erik van der Bij
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System architecture

Access to mezzanine EEPROM

Two ways of accessing the EEPROM on the mezzanine:

  • GN4124 via GPIO (implies bit-bang)
  • FPGA via the OpenCores I2C controller
    • Must boot the FPGA with a firmware that allows access to the mezzanine (system) I2C.

CSR memory map

  • Fixed range for each wishbone slaves and placed one after the other.
    • What if a slave needs more than the allocated range (memory) -> allocate more than one slot for a single slave?
  • Window equally shared among wishbone slaves.
    • Not optimal as the base addresses of the wishbone slaves will change if a slave is added.

FPGA boot

By default on the SPEC board the FPGA boots from Flash.
In most cases, the firmware will be loaded by the driver via GN4124 firmware loader interface.

M. Cattin