Multi-channel Time Interval Counter and fine delay generator
Project description
The goal of the project is to create a high-resolution TDC and fine delay generator using only open source software and hardware. We hope this design can become the basis of experimentation and collaboration in a wider community.
Several time interval measurement techniques will be explored in this project. One important family of solutions feeds input pulses into shaping filters followed by an ADC. By time-shifting the acquired waveforms in software, and maximizing correlation between two channels, one can figure out the time interval between two pulses.
Firstly, we made a data acquisition system. To optimise the precision, the transition from the analog to the digital world has to be as clean as possible. It is on this system that the different time measuring elements are added.
Acutal prototype features
| Parameter | Value |
|---|---|
| channels | 4 |
| Precision | < 5 ps RMS |
| Range | 10 ns |
| Input pulse voltage | 2.31 V to 3.3 V |
| Measurements rate | 1.5 Hz |
| Connectors | SMA @ 50 ohm |
| Clock source | Internal: 100 MHz oscillator |
| External: up to 125 MHz with an external clock |
The "brain" of the system is a MicroZed FPGA prototyping board. We designed an ADC board as a carrier card for the MicroZed.
The used ADC is the Analog Devices AD9253 .
Detailed project information
The ADC Board
- Board-features
- Quick-design-explanation
- Layout-explanation
- Testing-the-board
- Delay-measurements
- Thesis: Development of a high precision multi-channel time-to-digital converter
Reviews
The Filter Prototyping Board (Canceled project)
Software development
Related Stuff
- Octave-quick-tutorial-and-useful-links
- Other-TDC-projects
- MicroZed prototyping board
Contacts
General questions about the project
- Nicolas Boucquey - CERN
Project Status
| Date | Event |
|---|---|
| 01-02-2016 | Start working on project. |
| 15-02-2016 | Starting the first ADC board Design |
| 05-03-2016 | Finishing the first Design |
| 05-03-2016 | Starting the layout of the first ADC board |
| 12-04-2016 | Presentation of the project, design and layout at CERN |
| 15-04-2016 | Full design and layout review at CERN |
| 15-05-2016 | Start to update the schematics |
| 03-06-2016 | Schematic updated. Wait for review |
| 21-06-2016 | Review of the schematics |
| 27-06-2016 | Starting new layout |
| 05-07-2016 | Layout finished. Waiting for review |
| 13-07-2016 | Layout Review at CERN |
| 02-08-2016 | Layout corrected, first prototype ordered |
| 16-09-2016 | PCB mounted arrived and ready for debug |
| 21-09-2016 | Low noise filter build, tests started |
| 07-10-2016 | RMS error on the measurements : 3 ps |
8th of November 2016 - Nicolas Boucquey