The gateware topology is represented in figure 1. The ADC data are first
deserialised and aligned. Each channel has its own buffer and trigger.
The buffer stores continuously the data by looping back to the buffer
beginning once its end is reached. In the meanwhile, these data are also
compared to the threshold level in the trigger. Once the data is (for
example) higher than the threshold, the trigger sends a signal to the
buffer. This signal tells the buffer it has to stop erasing the new
Figure 1 - Topology for the Gateware. In blue are the component clocked
with the external clock. The red ones belong to the processing system
Once the record is done, the processing system takes the data out of the
buffer and process them in software.
The usual way to implement hardware registers and doing the
communication between hardware and software on the Zynq platform is
through the AXI protocol. To be able to use available open cores and
existing codes, the AXI is converted into Wishbone.
There are two clock domains. On one hand we have the sampling clock
domain and on the other hand we have the system clock domain.
The SPI communication with the ADC is done in software by using the
Finally, the thermometer is read using the one wire interface.
ADC Raw Output
The first stage of this core is the ISERDES (Input Serialiser
Deserialiser). To explain how it has been configured, we need to know
how the data are coming out of the ADC. It is possible to format these
output by configuring the ADC using the SPI bus. All the developed
hardware developed is based on the default
figure 2 - Raw data out of the ADC 
Each of the four input channels sends data on two separate DDR (Double
Data Rate) lanes. Then, the 16 bits of each frame is divided in two
serial flows of 8~bits arriving in parallel to our core. Even if the
frame is composed of 16~bits, the AD9253 is a 14 bits converter. The two
last frame bits are 0.
The maximum data rate is 1 Gbit/s (the highest frequency is 500 Hz). In
addition to these signal lines we have also one clock line and one frame
clock as represented on figure 2.
Deserialisation and Bit Alignement
The goal of the ISERDES is to deserialise these bits in the correct
order. It is always possible to shift the bits at the output of the
ISERDES by using the bitslip function. On each pulse of the bitslip, the
bits are shifted as represented on figure 3. It is then possible to
shift them until we get the right order at the output. The system does
not have enough information to determine if the frame has correctly been
reconstructed or not. To set it correctly, one solution would be to add
a push button to the board and allow the user to send bitslip pulses
until the frames are correctly
Figure 2 - DDR Bitsplit operations on one channel 
To automate this process, we decided to send the frame clock in the
ISERDES too. As we know that this signal should be a clock one, we can
then check if it has been correctly reconstructed at the ISERDES output.
If it is not well reconstructed, we send one bitslip pulse and check its
reconstruction again. The same bitslip signal is sent to all the inputs
and all the bits are shifted together. If the frame clock is correctly
reconstructed, we can be sure all the signals are correctly
As previously said, the ADC is only sending 14 useful bits. They are
converted in 16 bits before being send to the buffer/trigger stage. The
second complement sign convention must be kept during the conversion.
The easiest way to do this is by copying the 14 bit vector MSB two times
and adding them as msb for the 16 bits vector.
The buffer goal is to store the recorded data before sending them to the
PS. Their actual size is 1024 bytes for each. When the acquisition bit
in the control status register is set, the data are consecutively
written in the DPRAM. When the memory end is reached, the pointer is
placed at the memory beginning and the previous data are erased by the
new ones. When the frame record is triggered, the buffer stores the
pointer (trig_pos) value and computes the pointer value at which it
will stop erasing the previous data (wr_addr_last) (eq 1).
wr_addr_last = trig_pos - pretrigger
The DPRAM allows us to transmit the data from the sampling clock domain
to the system clock domain.
Start: Start recording.
Ready: Ready to transfer the data to the PS
Size : Read the buffer size. Has to be changed in the gateware.
Pretrigger: Set the pretrigger value.
Trigger Position: Returns the Trigger position.
Address: Write the address of the Data to be available in the
Data: Read the 16 bit data available on the given address.
The data are sent both in the buffer and in the trigger. Data records
can be triggered either on rising or falling edges of the incoming
signal. This can be chosen by configuring the polarity bit. The data are
compared to two threshold levels in a state
If we take the example of the positive polarity, to trigger the record,
the datum has first to be bigger than the low level trigger and then
bigger than the high level trigger without passing again beneath the
trigger low level.
For fast triggering, the low level trigger can be put to a very low
Enable : Enable the trigger.
Polarity : Select polarity. Rising edge if 0 and Falling edge
MASK : Select on which channel the record will be triggered by
Force : Force the trigger.
Triggered : Triggered Flag.
Threshold Low : Signed 16 bits low threshold value
Threshold High : Signed 16 bits high threshold value
One Wire Communication
The DS18B20 thermometer communicates with a one wire interface. Timing
constraints are critical in this protocol. For correct timing, the
parameters CDR_N and CDR_O have to be set according to the clock