MicroZed Design

Proposed Topology

The development of the application is done using the Vivado software. The planned topology is represented in figure 1. The two main blocks that are represented are the ADC Board and the Zynq platform. Only the components that interact with the FPGA are represented in the ADC Board Bloc.

First, the FPGA is used to interact with the ADC. This is done by two interfaces: a SPI bus and the data lines. The SPI interface allows us to change the size of the frames, the resolution, the phase of the data, etc. All these data are sent to the FPGA on two serial lanes for each channel. These data have to be demultiplexed using an ISERDES (Input Serializer Deserializer) core.

Figure 1 - Topology for the MicroZed Design

Then these data are compared with a threshold value. The data are not kept in memory while the sample value is under this threshold. The first sample kept in the memory corresponds to the first sample of the oscillating output of the filter. The following samples are also recorded and then sent to the memory via DMA (Direct Memory Access). At the same time, the PL sends an interrupt to the PS to aware it that the data are arrived. All these data have to be timestamped to be able to compare them with data coming from other channels.

Finally, to determine the TOA (Time Of Arrival) of our pulse, we have to send our clock synchronised pulse trough the same channel. To avoid as much jitter as possible, we add a flip flop at the FPGA output.

Nicolas Boucquey 24-08-2016