Skip to content

  • Projects
  • Groups
  • Snippets
  • Help
    • Loading...
  • Sign in
H
Hdlmake
  • Project
    • Project
    • Details
    • Activity
    • Cycle Analytics
  • Repository
    • Repository
    • Files
    • Commits
    • Branches
    • Tags
    • Contributors
    • Graph
    • Compare
    • Charts
  • Issues 12
    • Issues 12
    • List
    • Board
    • Labels
    • Milestones
  • Merge Requests 2
    • Merge Requests 2
  • Wiki
    • Wiki
  • image/svg+xml
    Discourse
    • Discourse
  • Members
    • Members
  • Collapse sidebar
  • Activity
  • Graph
  • Charts
  • Create a new issue
  • Commits
  • Issue Boards
  • Projects
  • Hdlmake
  • Issues

  • Open 6
  • Closed 34
  • All 40
New issue
Recent searches
  • Priority Created date Last updated Milestone Due date Popularity Label priority
  • Xilinx ISE: make project fails if project file exists
    #99 · opened Sep 11, 2019 by Dimitris Lampridis   bug
    • 0
    updated Sep 11, 2019
  • VHDL parser should create relations for package without library
    #12 · opened Nov 15, 2016 by Nicolas Chevillot   bug
    • 1
    updated Mar 30, 2019
  • multitline signal declaration generates wrong relations in VHDL
    #13 · opened Nov 14, 2016 by Nicolas Chevillot   bug
    • 0
    updated Feb 12, 2019
  • String Element inside $display Verilog function will be misinterpreted as module
    #17 · opened Jun 02, 2016 by Andreas Bergmann   bug
    • 2
    updated Mar 30, 2019
  • Relations missing for VHDL package to be used in system verilog
    #20 · opened Jun 01, 2016 by Nicolas Chevillot   bug
    • 6
    updated Feb 12, 2019
  • Parameter is misinterprated and misinterpreted as (missing) module
    #34 · opened Apr 13, 2016 by Andreas Bergmann (Consult)   bug
    • 1
    updated Mar 30, 2019