multitline signal declaration generates wrong relations in VHDL
following VHDL code:
-------
signal sig1, sig2,
sig3: std_logic;
-------
will generate a "use","module","std_logic" relation.
I suggest that the VHDL is preprocessed this way:
1) remove all comments
2) put everything on a single line
3) cut lines after each semicolon (optional)
this way the above piece of code does not generate a wrong relation