Relations missing for VHDL package to be used in system verilog
In case of mixed-language simulation, a VHDL file defining a package (library test, package this_package) generates the following relation: Provide package test.this_package
If we want to use this package from SystemVerilog file, we need to use
the following import:
and compile the SystemVerilog file using -L test to include the test library.
However the Verilog parser in this case will generate the following relation: Use package this_package
Therefore the dependency is not found.
The VHDL parser should in case of defining a package add the followinfg
Provide package test.this_package
Provide package this_package
so the dependency will be fulfilled